國立虎尾科技大學 |

登入

回首頁

A Jitter-Cleaning Fractional-N Frequ...

University of California, Los Angeles.

A Jitter-Cleaning Fractional-N Frequency Synthesizer with 10 Hz--40 kHz Digitally Programmable Loop Bandwidth.

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	A Jitter-Cleaning Fractional-N Frequency Synthesizer with 10 Hz--40 kHz Digitally Programmable Loop Bandwidth./
作者:	Yao, Chih-Wei.
面頁冊數:	118 p.
附註:	Source: Dissertation Abstracts International, Volume: 73-07, Section: B, page: .
Contained By:	Dissertation Abstracts International73-07B.
標題:	Engineering, Electronics and Electrical. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3502361
ISBN:	9781267252852

A Jitter-Cleaning Fractional-N Frequency Synthesizer with 10 Hz--40 kHz Digitally Programmable Loop Bandwidth.
Yao, Chih-Wei.

A Jitter-Cleaning Fractional-N Frequency Synthesizer with 10 Hz--40 kHz Digitally Programmable Loop Bandwidth. - 118 p.

Source: Dissertation Abstracts International, Volume: 73-07, Section: B, page: .

Thesis (Ph.D.)--University of California, Los Angeles, 2012.

This dissertation contains three parts. In the first part, the analysis and circuits of a jitter-cleaning fractional-N frequency synthesizer is presented. In the second part, a low phase noise and low I/Q mismatch quadrature VCO is presented. In the third part, a low phase noise digital PLL is presented.

ISBN: 9781267252852Subjects--Topical Terms:

845382
Engineering, Electronics and Electrical.

A Jitter-Cleaning Fractional-N Frequency Synthesizer with 10 Hz--40 kHz Digitally Programmable Loop Bandwidth.
LDR:02937nam 2200337 4500 001 712999
005 20121003100335.5
008 121101s2012 ||||||||||||||||| ||eng d
020 $a 9781267252852
035 $a (UMI)AAI3502361
035 $a AAI3502361
040 $a UMI $c UMI
100 1 $a Yao, Chih-Wei. $3 845569
245 1 2 $a A Jitter-Cleaning Fractional-N Frequency Synthesizer with 10 Hz--40 kHz Digitally Programmable Loop Bandwidth.
300 $a 118 p.
500 $a Source: Dissertation Abstracts International, Volume: 73-07, Section: B, page: .
500 $a Adviser: Alan N. Willson, Jr.
502 $a Thesis (Ph.D.)--University of California, Los Angeles, 2012.
520 $a This dissertation contains three parts. In the first part, the analysis and circuits of a jitter-cleaning fractional-N frequency synthesizer is presented. In the second part, a low phase noise and low I/Q mismatch quadrature VCO is presented. In the third part, a low phase noise digital PLL is presented.
520 $a For the first part, the design utilizes a dual-loop architecture, which is suitable for integration in an SoC environment. The primary loop is a digital PLL with a second-order noise shaping phase-error ADC. The secondary loop is a fractional-N PLL implementing the digitally controlled oscillator inside the primary loop, and it locks to an external clean reference clock to reduce the phase noise and to improve the frequency stability of the on-chip oscillator.
520 $a For the second part, a tail-tank coupling technique that combines two complementary differential LC-VCOs to form a quadrature LC-VCO is presented. This technique reduces phase noise by providing additional energy storages for noise redistribution and by canceling out most of the noise injected by transistors when they operate in the triode region. The resulting noise factor is close to the theoretical minimum value.
520 $a For the third part, a 2.8 to 3.2 GHz fractional-N digital PLL is presented. A divider with two-stage retiming improves linearity to reduce fractional spurs without increasing the in-band noise floor. An ADC is employed to boost TDC resolution by five times to achieve 2 ps effective resolution. A dither-less DCO with an inductively coupled fine-tune varactor bank improves tuning step-size to 20 kHz. With a 52 MHz reference clock and a loop-bandwidth of 950 kHz, this prototype achieves 230 fs rms jitter integrated from 1 kHz to 40 MHz offset while drawing 17 mW from a 1.8V supply. A FOM of -240.4 dB is achieved.
590 $a School code: 0031.
650 4 $a Engineering, Electronics and Electrical. $3 845382
690 $a 0544
710 2 $a University of California, Los Angeles. $b Electrical Engineering 0303. $3 845570
773 0 $t Dissertation Abstracts International $g 73-07B.
790 1 0 $a Willson, Alan N., Jr., $e advisor
790 1 0 $a Chang, Mau-Chung F. $e committee member
790 1 0 $a Pamarti, Sudhakar $e committee member
790 1 0 $a Ercegovac, Milos D. $e committee member
790 $a 0031
791 $a Ph.D.
792 $a 2012
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3502361

筆 0 讀者評論

多媒體

評論

新增評論分享你的心得

Export

取書館別