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Time-predictable architectures DUP_1
~
Uhrig, Sascha.
Time-predictable architectures DUP_1
紀錄類型:
書目-語言資料,印刷品 : Monograph/item
正題名/作者:
Time-predictable architectures DUP_1/ Christine Rochange, Sascha Uhrig, Pascal Sainrat.
作者:
Rochange, Christine.
其他作者:
Uhrig, Sascha.
出版者:
London, UK :ISTE, Ltd. ; : 2014.,
面頁冊數:
1 online resource.
標題:
Real-time data processing. -
電子資源:
http://onlinelibrary.wiley.com/book/10.1002/9781118790229
ISBN:
9781118790229 (electronic bk.)
Time-predictable architectures DUP_1
Rochange, Christine.
Time-predictable architectures DUP_1
[electronic resource] /Christine Rochange, Sascha Uhrig, Pascal Sainrat. - London, UK :ISTE, Ltd. ;2014. - 1 online resource. - Focus series. - Focus series..
Includes bibliographical references and index.
Real-Time Systems and Time Predictability / Christine Rochange, Sascha Uhrig, Pascal Sainrat -- Timing Analysis of Real-Time Systems / Christine Rochange, Sascha Uhrig, Pascal Sainrat -- Current Processor Architectures / Christine Rochange, Sascha Uhrig, Pascal Sainrat -- Memory Hierarchy / Christine Rochange, Sascha Uhrig, Pascal Sainrat -- Multicores / Christine Rochange, Sascha Uhrig, Pascal Sainrat -- Example Architectures / Christine Rochange, Sascha Uhrig, Pascal Sainrat.
ISBN: 9781118790229 (electronic bk.)
Standard No.: 10.1002/9781118790229doiSubjects--Topical Terms:
568181
Real-time data processing.
LC Class. No.: QA76.54
Dewey Class. No.: 004.33
Time-predictable architectures DUP_1
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http://onlinelibrary.wiley.com/book/10.1002/9781118790229
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