國立虎尾科技大學 |

Out-of-order parallel discrete event simulation for electronic system-level design

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Out-of-order parallel discrete event simulation for electronic system-level design/ by Weiwei Chen.
作者:	Chen, Weiwei.
出版者:	Cham :Springer International Publishing : : 2015.,
面頁冊數:	xix, 145 p. :ill. (some col.), digital ; : 24 cm.;
Contained By:	Springer eBooks
標題:	Systems on a chip - Design. -
電子資源:	http://dx.doi.org/10.1007/978-3-319-08753-5
ISBN:	9783319087535 (electronic bk.)

Out-of-order parallel discrete event simulation for electronic system-level design
Chen, Weiwei.

Out-of-order parallel discrete event simulation for electronic system-level design[electronic resource] /by Weiwei Chen. - Cham :Springer International Publishing :2015. - xix, 145 p. :ill. (some col.), digital ;24 cm.

Introduction -- The ConcurrenC Model of Computation -- Synchronous Parallel Discrete Event Simulation -- Out-of-order Parallel Discrete Event Simulation -- Optimized Out-of-order Parallel Discrete Event Simulation -- Comparison and Outlook -- Utilizing the Parallel Simulation Infrastructure -- Conclusions.

This book offers readers a set of new approaches and tools a set of tools and techniques for facing challenges in parallelization with design of embedded systems. It provides an advanced parallel simulation infrastructure for efficient and effective system-level model validation and development so as to build better products in less time. Since parallel discrete event simulation (PDES) has the potential to exploit the underlying parallel computational capability in today's multi-core simulation hosts, the author begins by reviewing the parallelization of discrete event simulation, identifying problems and solutions. She then describes out-of-order parallel discrete event simulation (OoO PDES), a novel approach for efficient validation of system-level designs by aggressively exploiting the parallel capabilities of todays' multi-core PCs. This approach enables readers to design simulators that can fully exploit the parallel processing capability of the multi-core system to achieve fast speed simulation, without loss of simulation and timing accuracy. Based on this parallel simulation infrastructure, the author further describes automatic approaches that help the designer quickly to narrow down the debugging targets in faulty ESL models with parallelism. Provides an introduction to electronic system-level (ESL) design, along with background on simulation execution semantics for ESL models; Discusses discrete event simulation, along with synchronous and out-of-order parallel discrete simulation approaches, including the underlying data structure, the scheduling algorithm, and the predictive static code analysis technique; Includes guidelines for choosing among different simulation and diagnosis approaches for models with different features; Presents the model analysis approaches to increase the observability for parallel ESL model development.

ISBN: 9783319087535 (electronic bk.)

Standard No.: 10.1007/978-3-319-08753-5doiSubjects--Topical Terms:

1062289
Systems on a chip
--Design.

LC Class. No.: TK7895.E42

Dewey Class. No.: 621.3815

Out-of-order parallel discrete event simulation for electronic system-level design
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520 $a This book offers readers a set of new approaches and tools a set of tools and techniques for facing challenges in parallelization with design of embedded systems. It provides an advanced parallel simulation infrastructure for efficient and effective system-level model validation and development so as to build better products in less time. Since parallel discrete event simulation (PDES) has the potential to exploit the underlying parallel computational capability in today's multi-core simulation hosts, the author begins by reviewing the parallelization of discrete event simulation, identifying problems and solutions. She then describes out-of-order parallel discrete event simulation (OoO PDES), a novel approach for efficient validation of system-level designs by aggressively exploiting the parallel capabilities of todays' multi-core PCs. This approach enables readers to design simulators that can fully exploit the parallel processing capability of the multi-core system to achieve fast speed simulation, without loss of simulation and timing accuracy. Based on this parallel simulation infrastructure, the author further describes automatic approaches that help the designer quickly to narrow down the debugging targets in faulty ESL models with parallelism. Provides an introduction to electronic system-level (ESL) design, along with background on simulation execution semantics for ESL models; Discusses discrete event simulation, along with synchronous and out-of-order parallel discrete simulation approaches, including the underlying data structure, the scheduling algorithm, and the predictive static code analysis technique; Includes guidelines for choosing among different simulation and diagnosis approaches for models with different features; Presents the model analysis approaches to increase the observability for parallel ESL model development.
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