國立虎尾科技大學 |

Microarchitecture of network-on-chip routers = a designer's perspective /

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Microarchitecture of network-on-chip routers/ by Giorgos Dimitrakopoulos, Anastasios Psarras, Ioannis Seitanidis.
其他題名:	a designer's perspective /
作者:	Dimitrakopoulos, Giorgos.
其他作者:	Psarras, Anastasios.
出版者:	New York, NY :Springer New York : : 2015.,
面頁冊數:	xiv, 175 p. :ill. (some col.), digital ; : 24 cm.;
Contained By:	Springer eBooks
標題:	Networks on a chip. -
電子資源:	http://dx.doi.org/10.1007/978-1-4614-4301-8
ISBN:	9781461443018 (electronic bk.)

Microarchitecture of network-on-chip routers = a designer's perspective /
Dimitrakopoulos, Giorgos.

Microarchitecture of network-on-chip routersa designer's perspective /[electronic resource] :by Giorgos Dimitrakopoulos, Anastasios Psarras, Ioannis Seitanidis. - New York, NY :Springer New York :2015. - xiv, 175 p. :ill. (some col.), digital ;24 cm.

Introduction to network-on-chip design -- Link-level flow control and buffering -- Baseline switching modules and routers -- Arbitration logic -- Pipelined wormhole routers -- Virtual-channel flow control and buffering -- Baseline virtual-channel based switching modules and routers -- High-speed allocators for VC-based routers -- Pipelined virtual-channel-based routers.

This book provides a unified overview of network-on-chip router micro-architecture, the corresponding design opportunities and challenges, and existing solutions to overcome these challenges. The discussion focuses on the heart of a NoC, the NoC router, and how it interacts with the rest of the system. Coverage includes both basic and advanced design techniques that cover the entire router design space including router organization, flow control, pipelined operation, buffering architectures, as well as allocators' structure and algorithms. Router micro-architectural options are presented in a step-by-step manner beginning from the basic design principles. Even highly sophisticated design alternatives are categorized and broken down to simpler pieces that can be understood easily and analyzed. This book is an invaluable reference for system, architecture, circuit, and EDA researchers and developers, who are interested in understanding the overall picture of NoC routers' architecture, the associated design challenges, and the available solutions. Designed pedagogically, explaining basic functionality of each NoC router and design block, relating it to the role it plays in the system; Performance-enhancing features are added in a step-by-step manner; Justifies and explains every design choice, including the less attractive options; Includes detailed examples presenting the flow of information inside the router on a cycle-by-cycle basis, highlighting the operation of each part under regular or worst-case traffic scenarios.

ISBN: 9781461443018 (electronic bk.)

Standard No.: 10.1007/978-1-4614-4301-8doiSubjects--Topical Terms:

782046
Networks on a chip.

LC Class. No.: TK5105.546

Dewey Class. No.: 621.381531

Microarchitecture of network-on-chip routers = a designer's perspective /
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520 $a This book provides a unified overview of network-on-chip router micro-architecture, the corresponding design opportunities and challenges, and existing solutions to overcome these challenges. The discussion focuses on the heart of a NoC, the NoC router, and how it interacts with the rest of the system. Coverage includes both basic and advanced design techniques that cover the entire router design space including router organization, flow control, pipelined operation, buffering architectures, as well as allocators' structure and algorithms. Router micro-architectural options are presented in a step-by-step manner beginning from the basic design principles. Even highly sophisticated design alternatives are categorized and broken down to simpler pieces that can be understood easily and analyzed. This book is an invaluable reference for system, architecture, circuit, and EDA researchers and developers, who are interested in understanding the overall picture of NoC routers' architecture, the associated design challenges, and the available solutions. Designed pedagogically, explaining basic functionality of each NoC router and design block, relating it to the role it plays in the system; Performance-enhancing features are added in a step-by-step manner; Justifies and explains every design choice, including the less attractive options; Includes detailed examples presenting the flow of information inside the router on a cycle-by-cycle basis, highlighting the operation of each part under regular or worst-case traffic scenarios.
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