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Arbitrary modeling of TSVs for 3D integrated circuits

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Arbitrary modeling of TSVs for 3D integrated circuits/ by Khaled Salah, Yehea Ismail, Alaa El-Rouby.
作者:	Salah, Khaled.
其他作者:	Ismail, Yehea.
出版者:	Cham :Springer International Publishing : : 2015.,
面頁冊數:	ix, 179 p. :ill. (some col.), digital ; : 24 cm.;
Contained By:	Springer eBooks
標題:	Three-dimensional integrated circuits - Mathematical models. -
電子資源:	http://dx.doi.org/10.1007/978-3-319-07611-9
ISBN:	9783319076119 (electronic bk.)

Arbitrary modeling of TSVs for 3D integrated circuits
Salah, Khaled.

Arbitrary modeling of TSVs for 3D integrated circuits[electronic resource] /by Khaled Salah, Yehea Ismail, Alaa El-Rouby. - Cham :Springer International Publishing :2015. - ix, 179 p. :ill. (some col.), digital ;24 cm. - Analog circuits and signal processing,1872-082X. - Analog circuits and signal processing..

Introduction: Work around Moore's Law -- 3D/TSV Enabling Technologies -- TSV Modeling and Analysis -- TSV Verification -- TSV Macro-Modeling Framework -- TSV Design Applications: TSV-Based On-Chip Spiral Inductor, TSV-Based On-Chip Wireless Communications and TSV-Based Bandpass Filter -- Imperfection in TSV Modeling -- New Trends in TSV -- TSV Fabrication -- Conclusions.

This book presents a wide-band and technology independent, SPICE-compatible RLC model for through-silicon vias (TSVs) in 3D integrated circuits. This model accounts for a variety of effects, including skin effect, depletion capacitance, and nearby contact effects. Readers will benefit from in-depth coverage of concepts and technology such as 3D integration, Macro modeling, dimensional analysis, and compact modeling, as well as closed form equations for the through silicon via parasitics. Concepts covered are demonstrated by using TSVs in applications such as a spiral inductor, and inductive-based communication system, and bandpass filtering. Introduces a robust model that captures accurately all the loss modes of a TSV, coupling parasitics between TSVs and the TSV nonlinear capacitance and resistance of the depletion region; Enables readers to use a model which is technology dependent and can be used for any TSV configuration; Reveals a novel on-chip wireless communication technique, based on TSV spiral inductors; Equips readers for fast parasitic extraction of TSVs for 3D IC design.

ISBN: 9783319076119 (electronic bk.)

Standard No.: 10.1007/978-3-319-07611-9doiSubjects--Topical Terms:

1062434
Three-dimensional integrated circuits
--Mathematical models.

LC Class. No.: TK7874.893

Dewey Class. No.: 621.3815

Arbitrary modeling of TSVs for 3D integrated circuits
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505 0 $a Introduction: Work around Moore's Law -- 3D/TSV Enabling Technologies -- TSV Modeling and Analysis -- TSV Verification -- TSV Macro-Modeling Framework -- TSV Design Applications: TSV-Based On-Chip Spiral Inductor, TSV-Based On-Chip Wireless Communications and TSV-Based Bandpass Filter -- Imperfection in TSV Modeling -- New Trends in TSV -- TSV Fabrication -- Conclusions.
520 $a This book presents a wide-band and technology independent, SPICE-compatible RLC model for through-silicon vias (TSVs) in 3D integrated circuits. This model accounts for a variety of effects, including skin effect, depletion capacitance, and nearby contact effects. Readers will benefit from in-depth coverage of concepts and technology such as 3D integration, Macro modeling, dimensional analysis, and compact modeling, as well as closed form equations for the through silicon via parasitics. Concepts covered are demonstrated by using TSVs in applications such as a spiral inductor, and inductive-based communication system, and bandpass filtering. Introduces a robust model that captures accurately all the loss modes of a TSV, coupling parasitics between TSVs and the TSV nonlinear capacitance and resistance of the depletion region; Enables readers to use a model which is technology dependent and can be used for any TSV configuration; Reveals a novel on-chip wireless communication technique, based on TSV spiral inductors; Equips readers for fast parasitic extraction of TSVs for 3D IC design.
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