國立虎尾科技大學 |

Silicon nanowire transistors

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Silicon nanowire transistors/ by Ahmet Bindal, Sotoudeh Hamedi-Hagh.
作者:	Bindal, Ahmet.
其他作者:	Hamedi-Hagh, Sotoudeh.
出版者:	Cham :Springer International Publishing : : 2016.,
面頁冊數:	xiv, 165 p. :ill., digital ; : 24 cm.;
Contained By:	Springer eBooks
標題:	Nanowires. -
電子資源:	http://dx.doi.org/10.1007/978-3-319-27177-4
ISBN:	9783319271774

Silicon nanowire transistors
Bindal, Ahmet.

Silicon nanowire transistors[electronic resource] /by Ahmet Bindal, Sotoudeh Hamedi-Hagh. - Cham :Springer International Publishing :2016. - xiv, 165 p. :ill., digital ;24 cm.

Dual Work Function Silicon Nanowire MOS Transistors -- Single Work Function Silicon Nanowire MOS Transistors -- Spice Modeling For Analog and Digital Applications -- High-Speed Analog Applications -- Radio Frequency (RF) Applications -- SRAM Mega Cell Design for Digital Applications -- Field-Programmable-Gate-Array (FPGA) -- Integrate-And-Fire Spiking (IFS) Neuron -- Direct Sequence Spread Spectrum (DSSS) Base-Band Transmitter.

This book describes the n and p-channel Silicon Nanowire Transistor (SNT) designs with single and dual-work functions, emphasizing low static and dynamic power consumption. The authors describe a process flow for fabrication and generate SPICE models for building various digital and analog circuits. These include an SRAM, a baseband spread spectrum transmitter, a neuron cell and a Field Programmable Gate Array (FPGA) platform in the digital domain, as well as high bandwidth single-stage and operational amplifiers, RF communication circuits in the analog domain, in order to show this technology's true potential for the next generation VLSI. Describes Silicon Nanowire (SNW) Transistors, as vertically constructed MOS n and p-channel transistors, with low static and dynamic power consumption and small layout footprint; Targets System-on-Chip (SoC) design, supporting very high transistor count (ULSI), minimal power consumption requiring inexpensive substrates for packaging; Enables fabrication of different types of memory on the same chip, such as capacitive cells and transistors with floating gates that can be used as DRAMs and Flash memories.

ISBN: 9783319271774

Standard No.: 10.1007/978-3-319-27177-4doiSubjects--Topical Terms:

568223
Nanowires.

LC Class. No.: TK7874.85

Dewey Class. No.: 621.3815

Silicon nanowire transistors
LDR:02509nam a2200313 a 4500 001 862538
003 DE-He213
005 20160824154337.0
006 m d
007 cr nn 008maaau
008 170720s2016 gw s 0 eng d
020 $a 9783319271774 $q (electronic bk.)
020 $a 9783319271750 $q (paper)
024 7 $a 10.1007/978-3-319-27177-4 $2 doi
035 $a 978-3-319-27177-4
040 $a GP $c GP
041 0 $a eng
050 4 $a TK7874.85
072 7 $a TJFC $2 bicssc
072 7 $a TEC008010 $2 bisacsh
082 0 4 $a 621.3815 $2 23
090 $a TK7874.85 $b .B612 2016
100 1 $a Bindal, Ahmet. $3 1105961
245 1 0 $a Silicon nanowire transistors $h [electronic resource] / $c by Ahmet Bindal, Sotoudeh Hamedi-Hagh.
260 $a Cham : $c 2016. $b Springer International Publishing : $b Imprint: Springer,
300 $a xiv, 165 p. : $b ill., digital ; $c 24 cm.
505 0 $a Dual Work Function Silicon Nanowire MOS Transistors -- Single Work Function Silicon Nanowire MOS Transistors -- Spice Modeling For Analog and Digital Applications -- High-Speed Analog Applications -- Radio Frequency (RF) Applications -- SRAM Mega Cell Design for Digital Applications -- Field-Programmable-Gate-Array (FPGA) -- Integrate-And-Fire Spiking (IFS) Neuron -- Direct Sequence Spread Spectrum (DSSS) Base-Band Transmitter.
520 $a This book describes the n and p-channel Silicon Nanowire Transistor (SNT) designs with single and dual-work functions, emphasizing low static and dynamic power consumption. The authors describe a process flow for fabrication and generate SPICE models for building various digital and analog circuits. These include an SRAM, a baseband spread spectrum transmitter, a neuron cell and a Field Programmable Gate Array (FPGA) platform in the digital domain, as well as high bandwidth single-stage and operational amplifiers, RF communication circuits in the analog domain, in order to show this technology's true potential for the next generation VLSI. Describes Silicon Nanowire (SNW) Transistors, as vertically constructed MOS n and p-channel transistors, with low static and dynamic power consumption and small layout footprint; Targets System-on-Chip (SoC) design, supporting very high transistor count (ULSI), minimal power consumption requiring inexpensive substrates for packaging; Enables fabrication of different types of memory on the same chip, such as capacitive cells and transistors with floating gates that can be used as DRAMs and Flash memories.
650 0 $a Nanowires. $3 568223
650 0 $a Nanosilicon. $3 897081
650 0 $a Transistors. $3 1091209
650 1 4 $a Engineering. $3 561152
650 2 4 $a Circuits and Systems. $3 670901
650 2 4 $a Electronic Circuits and Devices. $3 782968
650 2 4 $a Nanotechnology. $3 557660
700 1 $a Hamedi-Hagh, Sotoudeh. $3 1105962
710 2 $a SpringerLink (Online service) $3 593884
773 0 $t Springer eBooks
856 4 0 $u http://dx.doi.org/10.1007/978-3-319-27177-4
950 $a Engineering (Springer-11647)