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Heterogeneous and Scalable Sketch-based Framework for Big Data Acceleration on Low Power Embedded Cores.

Record Type:	Language materials, manuscript : Monograph/item
Title/Author:	Heterogeneous and Scalable Sketch-based Framework for Big Data Acceleration on Low Power Embedded Cores./
Author:	Kulkarni, Amey Mahesh.
Description:	1 online resource (149 pages)
Notes:	Source: Dissertation Abstracts International, Volume: 78-10(E), Section: B.
Contained By:	Dissertation Abstracts International78-10B(E).
Subject:	Engineering. -
Online resource:	click for full text (PQDT)
ISBN:	9781369807202

Heterogeneous and Scalable Sketch-based Framework for Big Data Acceleration on Low Power Embedded Cores.
Kulkarni, Amey Mahesh.

Heterogeneous and Scalable Sketch-based Framework for Big Data Acceleration on Low Power Embedded Cores. - 1 online resource (149 pages)

Source: Dissertation Abstracts International, Volume: 78-10(E), Section: B.

Thesis (Ph.D.)

Includes bibliographical references

Ever-growing IoT demands big data processing and cognitive computing on mobile and battery operated devices. However, big data processing on low power embedded cores is challenging due to their limited communication bandwidth and on-chip storage. Additionally, IoT and cloud-based computing demand low overhead security kernel to avoid data breaches. In this PhD research, we propose LESS -- Light-weight Encryption using Scalable Sketching techniques for data reduction and encryption. LESS is a heterogeneous framework which consists of three important kernels: 1. sketching module for data reduction, 2. an accelerator for efficient sketch recovery using scalable and parallel reconstruction architecture and 3. a host processor to perform post processing.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2018

Mode of access: World Wide Web

ISBN: 9781369807202Subjects--Topical Terms:

561152
Engineering.
Index Terms--Genre/Form:

554714
Electronic books.

Heterogeneous and Scalable Sketch-based Framework for Big Data Acceleration on Low Power Embedded Cores.
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245 1 0 $a Heterogeneous and Scalable Sketch-based Framework for Big Data Acceleration on Low Power Embedded Cores.
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300 $a 1 online resource (149 pages)
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500 $a Source: Dissertation Abstracts International, Volume: 78-10(E), Section: B.
500 $a Adviser: Tinoosh Mohsenin.
502 $a Thesis (Ph.D.) $c University of Maryland, Baltimore County $d 2017.
504 $a Includes bibliographical references
520 $a Ever-growing IoT demands big data processing and cognitive computing on mobile and battery operated devices. However, big data processing on low power embedded cores is challenging due to their limited communication bandwidth and on-chip storage. Additionally, IoT and cloud-based computing demand low overhead security kernel to avoid data breaches. In this PhD research, we propose LESS -- Light-weight Encryption using Scalable Sketching techniques for data reduction and encryption. LESS is a heterogeneous framework which consists of three important kernels: 1. sketching module for data reduction, 2. an accelerator for efficient sketch recovery using scalable and parallel reconstruction architecture and 3. a host processor to perform post processing.
520 $a One of the critical challenges in big data processing on embedded hardware platforms is to reconstruct the sketched data in real-time with stringent constraints on error bounds and hardware resources. In this dissertation, we explore Orthogonal Matching Pursuit (OMP) algorithm for sketch data recovery. OMP is a greedy algorithm with high computational complexity which has emerged as an important tool for signal recovery, dictionary learning and sparse data classification. We propose parallel and reconfigurable architecture for OMP algorithm and implement it on FPGA, ASIC, and embedded platforms including Nvidia TK1, and PENC many-core platform developed by EEHPC lab. All processing platforms are evaluated for execution time, energy efficiency, chip area, and throughput based on different frequencies, and different level of parallelism. Based on the result analysis, we propose Thresholding technique for OMP (tOMP) and Gradient Descent OMP (GDOMP) to reduce hardware complexity of OMP algorithm. To demonstrate reconstruction efficiency of proposed OMP modifications, we compare signal-to-reconstruction error rate (SRER), signal-to-noise ratio (PSNR), and Structural Similarity index (SSIM) of previously proposed matching pursuit algorithms. We implemented three different reconfigurable and parallel hardwares for OMP, tOMP and GDOMP algorithms on 65nm CMOS technology operating at 1V supply voltage. The post place and route analysis on area, power, and latency show that, tOMP requires 33% less reconstruction time, whereas GDOMP consumes 44% less chip area when compared to OMP ASIC implementation. Compared to previously published work, the best architecture achieves 2.1x improvement in Area-Delay product (ADP) and consumes 40% less energy.
520 $a To conclude this work we integrated the heterogeneous LESS framework with Hadoop MapReduce platform and evaluated for three different applications including multi-channel EEG seizure detection, face detection, and object identification. In the LESS framework, sketching module and host processing is performed on ARM CPU, and three different platforms including ASIC, PENC many-core, and ARM CPU are evaluated as an accelerator. For seizure detection application, LESS framework with PENC as an accelerator achieves up to 72% reduction in data transfers with approximately 2.1% and 2.9% degradation in sensitivity and specificity respectively. For face detection and object identification datasets, LESS framework with PENC as an accelerator achieves up to 48% reduction in data transfers with only 0.11% execution overhead and negligible energy overhead of 0.001% when tested for 2.6GB streaming input data. LESS framework achieves 2.25x higher throughput per watt and requires 2x lesser transfer time as compared to MapReduce platform for face detection and object identification application.
533 $a Electronic reproduction. $b Ann Arbor, Mich. : $c ProQuest, $d 2018
538 $a Mode of access: World Wide Web
650 4 $a Engineering. $3 561152
650 4 $a Computer engineering. $3 569006
650 4 $a Electrical engineering. $3 596380
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710 2 $a ProQuest Information and Learning Co. $3 1178819
710 2 $a University of Maryland, Baltimore County. $b Engineering, Computer. $3 1179338
773 0 $t Dissertation Abstracts International $g 78-10B(E).
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=10257394 $z click for full text (PQDT)