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Efficient and verifiable timing chan...
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Wang, Yao.
Efficient and verifiable timing channel protection for multi-core processors.
紀錄類型:
書目-語言資料,手稿 : Monograph/item
正題名/作者:
Efficient and verifiable timing channel protection for multi-core processors./
作者:
Wang, Yao.
面頁冊數:
1 online resource (205 pages)
附註:
Source: Dissertation Abstracts International, Volume: 78-06(E), Section: B.
Contained By:
Dissertation Abstracts International78-06B(E).
標題:
Computer engineering. -
電子資源:
click for full text (PQDT)
ISBN:
9781369560985
Efficient and verifiable timing channel protection for multi-core processors.
Wang, Yao.
Efficient and verifiable timing channel protection for multi-core processors.
- 1 online resource (205 pages)
Source: Dissertation Abstracts International, Volume: 78-06(E), Section: B.
Thesis (Ph.D.)
Includes bibliographical references
Modern computing systems are becoming increasingly vulnerable to timing.
Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2018
Mode of access: World Wide Web
ISBN: 9781369560985Subjects--Topical Terms:
569006
Computer engineering.
Index Terms--Genre/Form:
554714
Electronic books.
Efficient and verifiable timing channel protection for multi-core processors.
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Source: Dissertation Abstracts International, Volume: 78-06(E), Section: B.
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Adviser: Edward Suh.
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Thesis (Ph.D.)
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Cornell University
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2017.
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Includes bibliographical references
520
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Modern computing systems are becoming increasingly vulnerable to timing.
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channel attacks that leak confidential information through the timing of.
520
$a
microarchitectural events. Many timing channel attacks are caused.
520
$a
by the interference between different programs in the shared resources.
520
$a
of a multi-core processor. For example, an attacker program's cache lines.
520
$a
can be evicted by a victim program, which allows the attacker to infer.
520
$a
secret information about the victim. Timing channel attacks pose serious.
520
$a
threats to contemporary computing systems because they can bypass.
520
$a
traditional defense mechanisms such as access control. Previous.
520
$a
studies have even demonstrated a practical timing channel attack to recover.
520
$a
the keystrokes of a user in the commercial Amazon EC2 cloud.
520
$a
In this thesis, we explored new timing channel attacks and developed timing.
520
$a
channel protection schemes for some of the hardware resources in a multi-core.
520
$a
processor. Specifically, we discovered new timing channel attacks in the.
520
$a
shared on-chip networks and memory controllers. We proposed multiple.
520
$a
protection mechanisms for on-chip networks, caches and memory controllers.
520
$a
Our protection schemes cover three high-level approaches: bi-directional.
520
$a
protections, uni-directional protections and protections that trade off.
520
$a
security for performance. We evaluate our protection schemes and.
520
$a
show that the proposed schemes are effective against timing channel attacks.
520
$a
while achieving performance improvements over previous protection schemes.
520
$a
Finally, we implemented some of the protection mechanisms in RTL and used.
520
$a
SecVerilog to verify the information flow control in hardware. The results.
520
$a
show that the protection mechanisms indeed remove timing channels at the.
520
$a
gate level.
533
$a
Electronic reproduction.
$b
Ann Arbor, Mich. :
$c
ProQuest,
$d
2018
538
$a
Mode of access: World Wide Web
650
4
$a
Computer engineering.
$3
569006
650
4
$a
Computer science.
$3
573171
655
7
$a
Electronic books.
$2
local
$3
554714
690
$a
0464
690
$a
0984
710
2
$a
ProQuest Information and Learning Co.
$3
1178819
710
2
$a
Cornell University.
$b
Electrical & Computer Engrng.
$3
1179333
773
0
$t
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$g
78-06B(E).
856
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http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=10253735
$z
click for full text (PQDT)
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