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Gigabit Ethernet (FPGA Implementations).

ProQuest Information and Learning Co.

Gigabit Ethernet (FPGA Implementations).

紀錄類型:	書目-語言資料,手稿 : Monograph/item
正題名/作者:	Gigabit Ethernet (FPGA Implementations)./
作者:	Ghodke, Srinivas B.
面頁冊數:	1 online resource (69 pages)
附註:	Source: Masters Abstracts International, Volume: 50-02, page: 1194.
Contained By:	Masters Abstracts International50-02.
標題:	Electrical engineering. -
電子資源:	click for full text (PQDT)
ISBN:	9781124985398

Gigabit Ethernet (FPGA Implementations).
Ghodke, Srinivas B.

Gigabit Ethernet (FPGA Implementations). - 1 online resource (69 pages)

Source: Masters Abstracts International, Volume: 50-02, page: 1194.

Thesis (M.S.)

Includes bibliographical references

The Ethernet core is designed for implementation of CSMA/CD LAN in accordance with the IEEE 802.3 standards. The Gigabit Ethernet technology is the high speed networking standard. Actually there are very few devices in the market and they do not provide coding and encoding. Hence this project deals with 8b/10b ENDEC for Gigabit Ethernet. It's a FPGA implementation and VLSI design & verification. In order to meet fast time to market requirements today's complex digital system design are using FPGAs. This paper will show you the design of 8b/10b Encoder/Decoder for Gigabit Ethernet using Actel SX FPGA.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2018

Mode of access: World Wide Web

ISBN: 9781124985398Subjects--Topical Terms:

596380
Electrical engineering.
Index Terms--Genre/Form:

554714
Electronic books.

Gigabit Ethernet (FPGA Implementations).
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035 $a (MiAaPQ)AAI1504355
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040 $a MiAaPQ $b eng $c MiAaPQ
099 $a TUL $f hyy $c available through World Wide Web
100 1 $a Ghodke, Srinivas B. $3 1182016
245 1 0 $a Gigabit Ethernet (FPGA Implementations).
264 0 $c 2011
300 $a 1 online resource (69 pages)
336 $a text $b txt $2 rdacontent
337 $a computer $b c $2 rdamedia
338 $a online resource $b cr $2 rdacarrier
500 $a Source: Masters Abstracts International, Volume: 50-02, page: 1194.
500 $a Adviser: Reza Nekovei.
502 $a Thesis (M.S.) $c Texas A&M University - Kingsville $d 2011.
504 $a Includes bibliographical references
520 $a The Ethernet core is designed for implementation of CSMA/CD LAN in accordance with the IEEE 802.3 standards. The Gigabit Ethernet technology is the high speed networking standard. Actually there are very few devices in the market and they do not provide coding and encoding. Hence this project deals with 8b/10b ENDEC for Gigabit Ethernet. It's a FPGA implementation and VLSI design & verification. In order to meet fast time to market requirements today's complex digital system design are using FPGAs. This paper will show you the design of 8b/10b Encoder/Decoder for Gigabit Ethernet using Actel SX FPGA.
520 $a VHDL is a high performance language for implementation and simulation. It integrates computation visualization and programming in an easy to use environment. VHDL is therefore built on a foundation of sophisticated language in which the basic element can implement it and verify it for hardware implementation.
520 $a Active HDL software is used for simulation and optimization of synthesizable VHDL code. This software is also used to verify the code generated in other applications.
533 $a Electronic reproduction. $b Ann Arbor, Mich. : $c ProQuest, $d 2018
538 $a Mode of access: World Wide Web
650 4 $a Electrical engineering. $3 596380
650 4 $a Robotics. $3 561941
650 4 $a Computer science. $3 573171
655 7 $a Electronic books. $2 local $3 554714
690 $a 0544
690 $a 0771
690 $a 0984
710 2 $a ProQuest Information and Learning Co. $3 1178819
710 2 $a Texas A&M University - Kingsville. $3 845674
773 0 $t Masters Abstracts International $g 50-02.
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=1504355 $z click for full text (PQDT)

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