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Dual Application ADC using Three Calibration Techniques in 10nm Technology.

Record Type:	Language materials, manuscript : Monograph/item
Title/Author:	Dual Application ADC using Three Calibration Techniques in 10nm Technology./
Author:	Schmelter, Brooke.
Description:	1 online resource (51 pages)
Notes:	Source: Masters Abstracts International, Volume: 57-01.
Contained By:	Masters Abstracts International57-01(E).
Subject:	Electrical engineering. -
Online resource:	click for full text (PQDT)
ISBN:	9780355496178

Dual Application ADC using Three Calibration Techniques in 10nm Technology.
Schmelter, Brooke.

Dual Application ADC using Three Calibration Techniques in 10nm Technology. - 1 online resource (51 pages)

Source: Masters Abstracts International, Volume: 57-01.

Thesis (M.S.)

Includes bibliographical references

In this work, a 12-bit ADC with three types of calibration is proposed for high speed security applications as well as a precision application. This converter performs for both applications because it satisfies all the necessary specifications such as minimal device mismatch and offset, programmability to decrease aging effects, high SNR for increased ENOB and fast conversion rate. The designed converter implements three types of calibration necessary for offset and gain error, including: a correlated double sampling integrator used in the first stage of the ADC, a power up auto zero technique implemented in the digital code to store any offset and subtract out if necessary, and an automatic startup and manual calibration to control the common mode voltages. The proposed ADC was designed in Intel's 10nm technology. This ADC is designed to monitor DC voltages for the precision and high speed applications. The conversion rate of the analog to digital converter is programmable to 7mus or 910ns, depending on the precision or high speed application, respectively. The range of the input and reference supply is 0 to 1.25V. The ADC is designed in Intel 10nm technology using a 1.8V supply consuming an area of 0.0705mm 2. This thesis explores challenges of designing a dual-purpose analog to digital converter, which include: 1.) increased offset in 10nm technology, 2.) dual application ADC that can be accurate and fast, 3.) reducing the parasitic capacitance of the ADC, and 4.) gain error that occurs in ADCs.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2018

Mode of access: World Wide Web

ISBN: 9780355496178Subjects--Topical Terms:

596380
Electrical engineering.
Index Terms--Genre/Form:

554714
Electronic books.

Dual Application ADC using Three Calibration Techniques in 10nm Technology.
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020 $a 9780355496178
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035 $a AAI10622573
040 $a MiAaPQ $b eng $c MiAaPQ
099 $a TUL $f hyy $c available through World Wide Web
100 1 $a Schmelter, Brooke. $3 1184124
245 1 0 $a Dual Application ADC using Three Calibration Techniques in 10nm Technology.
264 0 $c 2017
300 $a 1 online resource (51 pages)
336 $a text $b txt $2 rdacontent
337 $a computer $b c $2 rdamedia
338 $a online resource $b cr $2 rdacarrier
500 $a Source: Masters Abstracts International, Volume: 57-01.
500 $a Adviser: Bertan Bakkaloglu.
502 $a Thesis (M.S.) $c Arizona State University $d 2017.
504 $a Includes bibliographical references
520 $a In this work, a 12-bit ADC with three types of calibration is proposed for high speed security applications as well as a precision application. This converter performs for both applications because it satisfies all the necessary specifications such as minimal device mismatch and offset, programmability to decrease aging effects, high SNR for increased ENOB and fast conversion rate. The designed converter implements three types of calibration necessary for offset and gain error, including: a correlated double sampling integrator used in the first stage of the ADC, a power up auto zero technique implemented in the digital code to store any offset and subtract out if necessary, and an automatic startup and manual calibration to control the common mode voltages. The proposed ADC was designed in Intel's 10nm technology. This ADC is designed to monitor DC voltages for the precision and high speed applications. The conversion rate of the analog to digital converter is programmable to 7mus or 910ns, depending on the precision or high speed application, respectively. The range of the input and reference supply is 0 to 1.25V. The ADC is designed in Intel 10nm technology using a 1.8V supply consuming an area of 0.0705mm 2. This thesis explores challenges of designing a dual-purpose analog to digital converter, which include: 1.) increased offset in 10nm technology, 2.) dual application ADC that can be accurate and fast, 3.) reducing the parasitic capacitance of the ADC, and 4.) gain error that occurs in ADCs.
533 $a Electronic reproduction. $b Ann Arbor, Mich. : $c ProQuest, $d 2018
538 $a Mode of access: World Wide Web
650 4 $a Electrical engineering. $3 596380
655 7 $a Electronic books. $2 local $3 554714
690 $a 0544
710 2 $a ProQuest Information and Learning Co. $3 1178819
710 2 $a Arizona State University. $b Electrical Engineering. $3 845389
773 0 $t Masters Abstracts International $g 57-01(E).
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=10622573 $z click for full text (PQDT)