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Time-Based, Low-Power, Low-Offset 5-...
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ProQuest Information and Learning Co.
Time-Based, Low-Power, Low-Offset 5-Bit 1 Gs/S Flash ADC Design in 65nm CMOS Technology.
Record Type:
Language materials, manuscript : Monograph/item
Title/Author:
Time-Based, Low-Power, Low-Offset 5-Bit 1 Gs/S Flash ADC Design in 65nm CMOS Technology./
Author:
Nasrollahpour, Mehdi.
Description:
1 online resource (76 pages)
Notes:
Source: Masters Abstracts International, Volume: 57-01.
Contained By:
Masters Abstracts International57-01(E).
Subject:
Electrical engineering. -
Online resource:
click for full text (PQDT)
ISBN:
9780355350470
Time-Based, Low-Power, Low-Offset 5-Bit 1 Gs/S Flash ADC Design in 65nm CMOS Technology.
Nasrollahpour, Mehdi.
Time-Based, Low-Power, Low-Offset 5-Bit 1 Gs/S Flash ADC Design in 65nm CMOS Technology.
- 1 online resource (76 pages)
Source: Masters Abstracts International, Volume: 57-01.
Thesis (M.S.)
Includes bibliographical references
Low-power, medium resolution, high-speed analog-to-digital converters (ADCs) have always been important block which have abundant applications such as digital signal processors (DSP), imaging sensors, environmental and biomedical monitoring devices. This study presents a low power Flash ADC designed in nanometer complementary metal-oxide semiconductors (CMOS) technology. Time analysis on the output delay of the comparators helps to generate one more bit. The proposed technique reduced the power consumption and chip area substantially in comparison to the previous state-of-the-art work. The proposed ADC was developed in TSMC 65nm CMOS technology. The offset cancellation technique was embedded in the proposed comparator to decrement the static offset of the comparator. Moreover, one more bit was generated without using extra comparators. The proposed ADC achieved 4.1 bits ENOB at input Nyquist frequency. The simulated differential and integral non-linearity static tests were equal to +0.26/-0.17 and +0.22/-0.15, respectively. The ADC consumed 7.7 mW at 1 GHz sampling frequency, achieving 415 fJ/Convstep Figure of Merit (FoM).
Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2018
Mode of access: World Wide Web
ISBN: 9780355350470Subjects--Topical Terms:
596380
Electrical engineering.
Index Terms--Genre/Form:
554714
Electronic books.
Time-Based, Low-Power, Low-Offset 5-Bit 1 Gs/S Flash ADC Design in 65nm CMOS Technology.
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Time-Based, Low-Power, Low-Offset 5-Bit 1 Gs/S Flash ADC Design in 65nm CMOS Technology.
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San Jose State University
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Low-power, medium resolution, high-speed analog-to-digital converters (ADCs) have always been important block which have abundant applications such as digital signal processors (DSP), imaging sensors, environmental and biomedical monitoring devices. This study presents a low power Flash ADC designed in nanometer complementary metal-oxide semiconductors (CMOS) technology. Time analysis on the output delay of the comparators helps to generate one more bit. The proposed technique reduced the power consumption and chip area substantially in comparison to the previous state-of-the-art work. The proposed ADC was developed in TSMC 65nm CMOS technology. The offset cancellation technique was embedded in the proposed comparator to decrement the static offset of the comparator. Moreover, one more bit was generated without using extra comparators. The proposed ADC achieved 4.1 bits ENOB at input Nyquist frequency. The simulated differential and integral non-linearity static tests were equal to +0.26/-0.17 and +0.22/-0.15, respectively. The ADC consumed 7.7 mW at 1 GHz sampling frequency, achieving 415 fJ/Convstep Figure of Merit (FoM).
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Ann Arbor, Mich. :
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ProQuest,
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2018
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Mode of access: World Wide Web
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ProQuest Information and Learning Co.
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click for full text (PQDT)
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