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Statistical Estimator Aided SAR ADC ...

Ganesh, Archana.

Statistical Estimator Aided SAR ADC Design for Noise and Mismatch Suppression.

紀錄類型:	書目-語言資料,手稿 : Monograph/item
正題名/作者:	Statistical Estimator Aided SAR ADC Design for Noise and Mismatch Suppression./
作者:	Ganesh, Archana.
面頁冊數:	1 online resource (76 pages)
附註:	Source: Masters Abstracts International, Volume: 57-05.
Contained By:	Masters Abstracts International57-05(E).
標題:	Electrical engineering. -
電子資源:	click for full text (PQDT)
ISBN:	9780355679014

Statistical Estimator Aided SAR ADC Design for Noise and Mismatch Suppression.
Ganesh, Archana.

Statistical Estimator Aided SAR ADC Design for Noise and Mismatch Suppression. - 1 online resource (76 pages)

Source: Masters Abstracts International, Volume: 57-05.

Thesis (M.S.)

Includes bibliographical references

In this thesis, a statistical estimator based successive approximation register (SAR) analog to digital converter (ADC) is designed. This statistical estimator works based on maximum likelihood estimation (MLE) principle to compute the estimations. It estimates thermal noise of comparator and quantization noise. It also estimates the capacitive mismatch in the digital to analog converter (DAC). The estimated value is subtracted from output. This design aims to improve resolution and energy efficiency when compared to the conventional designs. For a 10-bit SAR ADC 63dB signal to noise distortion ratio (SNDR) is obtained for 1V supply voltage and 1.28MHz sampling frequency. The figure of merit (FOM) obtained is 13.86fJ/step. The circuits are designed in TSMC 65nm technology using Cadence and the computations and interpretations is done using MATLAB.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2018

Mode of access: World Wide Web

ISBN: 9780355679014Subjects--Topical Terms:

596380
Electrical engineering.
Index Terms--Genre/Form:

554714
Electronic books.

Statistical Estimator Aided SAR ADC Design for Noise and Mismatch Suppression.
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100 1 $a Ganesh, Archana. $3 1184131
245 1 0 $a Statistical Estimator Aided SAR ADC Design for Noise and Mismatch Suppression.
264 0 $c 2018
300 $a 1 online resource (76 pages)
336 $a text $b txt $2 rdacontent
337 $a computer $b c $2 rdamedia
338 $a online resource $b cr $2 rdacarrier
500 $a Source: Masters Abstracts International, Volume: 57-05.
500 $a Adviser: Arindam Sanyal.
502 $a Thesis (M.S.) $c State University of New York at Buffalo $d 2018.
504 $a Includes bibliographical references
520 $a In this thesis, a statistical estimator based successive approximation register (SAR) analog to digital converter (ADC) is designed. This statistical estimator works based on maximum likelihood estimation (MLE) principle to compute the estimations. It estimates thermal noise of comparator and quantization noise. It also estimates the capacitive mismatch in the digital to analog converter (DAC). The estimated value is subtracted from output. This design aims to improve resolution and energy efficiency when compared to the conventional designs. For a 10-bit SAR ADC 63dB signal to noise distortion ratio (SNDR) is obtained for 1V supply voltage and 1.28MHz sampling frequency. The figure of merit (FOM) obtained is 13.86fJ/step. The circuits are designed in TSMC 65nm technology using Cadence and the computations and interpretations is done using MATLAB.
533 $a Electronic reproduction. $b Ann Arbor, Mich. : $c ProQuest, $d 2018
538 $a Mode of access: World Wide Web
650 4 $a Electrical engineering. $3 596380
655 7 $a Electronic books. $2 local $3 554714
690 $a 0544
710 2 $a ProQuest Information and Learning Co. $3 1178819
710 2 $a State University of New York at Buffalo. $b Electrical Engineering. $3 845470
773 0 $t Masters Abstracts International $g 57-05(E).
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=10682624 $z click for full text (PQDT)

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