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Single-Ended Rail-to-Rail Low Power ...

Chen, Ping-Liang.

Single-Ended Rail-to-Rail Low Power SAR ADC Design.

紀錄類型:	書目-語言資料,手稿 : Monograph/item
正題名/作者:	Single-Ended Rail-to-Rail Low Power SAR ADC Design./
作者:	Chen, Ping-Liang.
面頁冊數:	1 online resource (89 pages)
附註:	Source: Masters Abstracts International, Volume: 55-01.
Contained By:	Masters Abstracts International55-01(E).
標題:	Electrical engineering. -
電子資源:	click for full text (PQDT)
ISBN:	9781321921007

Single-Ended Rail-to-Rail Low Power SAR ADC Design.
Chen, Ping-Liang.

Single-Ended Rail-to-Rail Low Power SAR ADC Design. - 1 online resource (89 pages)

Source: Masters Abstracts International, Volume: 55-01.

Thesis (M.S.)

Includes bibliographical references

In this thesis, a novel dynamic comparator is proposed and implemented using the low power SAR ADC architecture. A bootstrapping technique is used within the sample-and-hold circuit to ensure simplicity and low power operation with a sufficient bandwidth. The dynamic latched-comparator reduces the power consumption and its PMOS and NMOS differential input pairs provide the rail-to-rail input range. The higher degree of dispersion from the binary-weighted capacitor array is used in the design to improve the mismatch error. The design was fabricated using the ON-Semi C5N process. It has a 3 metal layers and 2 poly layers, and a high resistance layer. The typical threshold voltages for NMOS and PMOS are 0.8 and -0.9, respectively. The process is optimized for 5 Volts mixed-signal application according to the foundry.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2018

Mode of access: World Wide Web

ISBN: 9781321921007Subjects--Topical Terms:

596380
Electrical engineering.
Index Terms--Genre/Form:

554714
Electronic books.

Single-Ended Rail-to-Rail Low Power SAR ADC Design.
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020 $a 9781321921007
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099 $a TUL $f hyy $c available through World Wide Web
100 1 $a Chen, Ping-Liang. $3 1184160
245 1 0 $a Single-Ended Rail-to-Rail Low Power SAR ADC Design.
264 0 $c 2015
300 $a 1 online resource (89 pages)
336 $a text $b txt $2 rdacontent
337 $a computer $b c $2 rdamedia
338 $a online resource $b cr $2 rdacarrier
500 $a Source: Masters Abstracts International, Volume: 55-01.
500 $a Adviser: Albert H. Titus.
502 $a Thesis (M.S.) $c State University of New York at Buffalo $d 2015.
504 $a Includes bibliographical references
520 $a In this thesis, a novel dynamic comparator is proposed and implemented using the low power SAR ADC architecture. A bootstrapping technique is used within the sample-and-hold circuit to ensure simplicity and low power operation with a sufficient bandwidth. The dynamic latched-comparator reduces the power consumption and its PMOS and NMOS differential input pairs provide the rail-to-rail input range. The higher degree of dispersion from the binary-weighted capacitor array is used in the design to improve the mismatch error. The design was fabricated using the ON-Semi C5N process. It has a 3 metal layers and 2 poly layers, and a high resistance layer. The typical threshold voltages for NMOS and PMOS are 0.8 and -0.9, respectively. The process is optimized for 5 Volts mixed-signal application according to the foundry.
533 $a Electronic reproduction. $b Ann Arbor, Mich. : $c ProQuest, $d 2018
538 $a Mode of access: World Wide Web
650 4 $a Electrical engineering. $3 596380
655 7 $a Electronic books. $2 local $3 554714
690 $a 0544
710 2 $a ProQuest Information and Learning Co. $3 1178819
710 2 $a State University of New York at Buffalo. $b Electrical Engineering. $3 845470
773 0 $t Masters Abstracts International $g 55-01(E).
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=1594693 $z click for full text (PQDT)

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