國立虎尾科技大學 |

Design of CMOS integrated phase -locked loops for multi-gigabits serial data links.

紀錄類型:	書目-語言資料,手稿 : Monograph/item
正題名/作者:	Design of CMOS integrated phase -locked loops for multi-gigabits serial data links./
作者:	Cheng, Shanfeng.
面頁冊數:	1 online resource (188 pages)
附註:	Source: Dissertation Abstracts International, Volume: 67-12, Section: B, page: 7255.
Contained By:	Dissertation Abstracts International67-12B.
標題:	Electrical engineering. -
電子資源:	click for full text (PQDT)
ISBN:	9781109849523

Design of CMOS integrated phase -locked loops for multi-gigabits serial data links.
Cheng, Shanfeng.

Design of CMOS integrated phase -locked loops for multi-gigabits serial data links. - 1 online resource (188 pages)

Source: Dissertation Abstracts International, Volume: 67-12, Section: B, page: 7255.

Thesis (Ph.D.)

Includes bibliographical references

High-speed serial data links are quickly gaining in popularity and replacing the conventional parallel data links in recent years when the data rate of communication exceeds one gigabits per second. Compared with parallel data links, serial data links are able to achieve higher data rate and longer transfer distance. This dissertation is focused on the design of CMOS integrated phase-locked loops (PLLs) and relevant building blocks used in multi-gigabits serial data link transceivers.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2018

Mode of access: World Wide Web

ISBN: 9781109849523Subjects--Topical Terms:

596380
Electrical engineering.
Index Terms--Genre/Form:

554714
Electronic books.

Design of CMOS integrated phase -locked loops for multi-gigabits serial data links.
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100 1 $a Cheng, Shanfeng. $3 1184164
245 1 0 $a Design of CMOS integrated phase -locked loops for multi-gigabits serial data links.
264 0 $c 2006
300 $a 1 online resource (188 pages)
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500 $a Source: Dissertation Abstracts International, Volume: 67-12, Section: B, page: 7255.
500 $a Adviser: Jose Silva-Martinez.
502 $a Thesis (Ph.D.) $c Texas A&M University $d 2006.
504 $a Includes bibliographical references
520 $a High-speed serial data links are quickly gaining in popularity and replacing the conventional parallel data links in recent years when the data rate of communication exceeds one gigabits per second. Compared with parallel data links, serial data links are able to achieve higher data rate and longer transfer distance. This dissertation is focused on the design of CMOS integrated phase-locked loops (PLLs) and relevant building blocks used in multi-gigabits serial data link transceivers.
520 $a Firstly, binary phase-locked loops (BPLLs, i.e., PLLs based on binary phase detectors) are modeled and analyzed. The steady-state behavior of BPLLs is derived with combined discrete-time and continuous-time analysis. The jitter performance characteristics of BPLLs are analyzed. Secondly, a 10 Gbps clock and data recovery (CDR) chip for SONET OC-192, the mainstream standard for optical serial data links, is presented. The CDR is based on a novel referenceless dual-loop half-rate architecture. It includes a binary phase-locked loop based on a quad-level phase detector and a linear frequency-locked loop based on a linear frequency detector. The proposed architecture enables the CDR to achieve large locking range and small jitter generation at the same time. The prototype is implemented in 0.18 mum CMOS technology and consumes 250 mW under 1.8 V supply. The jitter generation is 0.5 ps-rms and 4.8 ps-pp. The jitter peaking and jitter tolerance performance exceeds the specifications defined by SONET OC-192 standard. Thirdly, a fully-differential divide-by-eight injection-locked frequency divider with low power dissipation is presented. The frequency divider consists of a four-stage ring of CML (current mode logic) latches. It has a maximum operating frequency of 18 GHz. The ratio of locking range over center frequency is up to 50%. The prototype chip is implemented in 0.18 mum CMOS technology and consumes 3.6 mW under 1.8 V supply. Lastly, the design and optimization techniques of fully differential charge pumps are discussed. Techniques are proposed to minimize the nonidealities associated with a fully differential charge pump, including differential mismatch, output current variation, low-speed glitches and high-speed glitches. The performance improvement brought by the techniques is verified with simulations of schematics designed in 0.35 mum CMOS technology.
533 $a Electronic reproduction. $b Ann Arbor, Mich. : $c ProQuest, $d 2018
538 $a Mode of access: World Wide Web
650 4 $a Electrical engineering. $3 596380
655 7 $a Electronic books. $2 local $3 554714
690 $a 0544
710 2 $a ProQuest Information and Learning Co. $3 1178819
710 2 $a Texas A&M University. $3 845439
773 0 $t Dissertation Abstracts International $g 67-12B.
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3246367 $z click for full text (PQDT)