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Low-power techniques for high-performance pipelined analog to digital converter.

Record Type:	Language materials, manuscript : Monograph/item
Title/Author:	Low-power techniques for high-performance pipelined analog to digital converter./
Author:	Lee, Byung-Geun.
Description:	1 online resource (97 pages)
Notes:	Source: Dissertation Abstracts International, Volume: 68-12, Section: B, page: 8257.
Contained By:	Dissertation Abstracts International68-12B.
Subject:	Electrical engineering. -
Online resource:	click for full text (PQDT)
ISBN:	9780549359647

Low-power techniques for high-performance pipelined analog to digital converter.
Lee, Byung-Geun.

Low-power techniques for high-performance pipelined analog to digital converter. - 1 online resource (97 pages)

Source: Dissertation Abstracts International, Volume: 68-12, Section: B, page: 8257.

Thesis (Ph.D.)

Includes bibliographical references

Low-power and small size analog to digital converters (ADCs) are the strategic building blocks in state of the art mobile wireless communication systems. Various techniques have been developed to reduce both power consumption and die area of the ADC. Among these, the opamp-sharing technique shows the most promise. In opamp-sharing, power and die area are saved by sharing one opamp between two successive pipeline stages. However, this technique suffers from the well-known memory effect drawback due to the absence of the reset phase that discharges the opamp's input parasitics.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2018

Mode of access: World Wide Web

ISBN: 9780549359647Subjects--Topical Terms:

596380
Electrical engineering.
Index Terms--Genre/Form:

554714
Electronic books.

Low-power techniques for high-performance pipelined analog to digital converter.
LDR:03239ntm a2200361Ki 4500 001 912005
005 20180605073452.5
006 m o u
007 cr mn||||a|a||
008 190606s2007 xx obm 000 0 eng d
020 $a 9780549359647
035 $a (MiAaPQ)AAI3291207
035 $a (MiAaPQ)utexas:3884
035 $a AAI3291207
040 $a MiAaPQ $b eng $c MiAaPQ
099 $a TUL $f hyy $c available through World Wide Web
100 1 $a Lee, Byung-Geun. $3 1184165
245 1 0 $a Low-power techniques for high-performance pipelined analog to digital converter.
264 0 $c 2007
300 $a 1 online resource (97 pages)
336 $a text $b txt $2 rdacontent
337 $a computer $b c $2 rdamedia
338 $a online resource $b cr $2 rdacarrier
500 $a Source: Dissertation Abstracts International, Volume: 68-12, Section: B, page: 8257.
500 $a Adviser: Jonathan W. Valvano.
502 $a Thesis (Ph.D.) $c The University of Texas at Austin $d 2007.
504 $a Includes bibliographical references
520 $a Low-power and small size analog to digital converters (ADCs) are the strategic building blocks in state of the art mobile wireless communication systems. Various techniques have been developed to reduce both power consumption and die area of the ADC. Among these, the opamp-sharing technique shows the most promise. In opamp-sharing, power and die area are saved by sharing one opamp between two successive pipeline stages. However, this technique suffers from the well-known memory effect drawback due to the absence of the reset phase that discharges the opamp's input parasitics.
520 $a In this dissertation, this drawback is solved by introducing a discharge phase before the opamp is used for the pipeline stages without compromising speed and resolution of the ADC. Further power and area reduction is achieved by using a capacitor-sharing technique. This technique reduces the effective load capacitance of the opamp by reusing the charge on the feedback capacitor for the MDAC operation of the following stage, resulting in faster settling without increasing opamp power. The proposed low input-capacitance variable- gm opamp also helps to reduce the memory effect and improves the settling behavior of the stage output by increasing the bandwidth of the opamp while input parasitics of the opamp are kept small.
520 $a The prototype designs of a 10-bit 50MSample/s pipelined ADC and a 14-bit 100MSample/s pipelined ADC implemented in 0.18mum CMOS technology demonstrate the effectiveness of the proposed techniques. The first ADC achieves 56.2dB SNDR and 72.7dB SFDR for a Nyquist input at full sampling rate while consuming 12 mW from a 1.8-V supply. The FOM, defined as, power2ENOB&dot;Fs , is 0.46 pJ/step with Fin = 24.5MHz at 50MS/s. The second ADC achieves 72.4dB SNR and 88.5dB SFDR at 100MS/s with a 46MHz input and consumes 230mW from a 3V supply. The FOM of the second ADC is 0.69 pJ/step with Fin = 46MHz at 100MS/s.
533 $a Electronic reproduction. $b Ann Arbor, Mich. : $c ProQuest, $d 2018
538 $a Mode of access: World Wide Web
650 4 $a Electrical engineering. $3 596380
655 7 $a Electronic books. $2 local $3 554714
690 $a 0544
710 2 $a ProQuest Information and Learning Co. $3 1178819
710 2 $a The University of Texas at Austin. $b ECE. $3 1184166
773 0 $t Dissertation Abstracts International $g 68-12B.
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3291207 $z click for full text (PQDT)