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Analog integrated circuit design techniques for high-speed signal processing in communications systems.

Record Type:	Language materials, manuscript : Monograph/item
Title/Author:	Analog integrated circuit design techniques for high-speed signal processing in communications systems./
Author:	Hernandez Garduno, David.
Description:	1 online resource (143 pages)
Notes:	Source: Dissertation Abstracts International, Volume: 69-01, Section: B, page: 5430.
Contained By:	Dissertation Abstracts International69-01B.
Subject:	Electrical engineering. -
Online resource:	click for full text (PQDT)
ISBN:	9780549416531

Analog integrated circuit design techniques for high-speed signal processing in communications systems.
Hernandez Garduno, David.

Analog integrated circuit design techniques for high-speed signal processing in communications systems. - 1 online resource (143 pages)

Source: Dissertation Abstracts International, Volume: 69-01, Section: B, page: 5430.

Thesis (Ph.D.)

Includes bibliographical references

This work presents design techniques for the implementation of high-speed analog integrated circuits for wireless and wireline communications systems.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2018

Mode of access: World Wide Web

ISBN: 9780549416531Subjects--Topical Terms:

596380
Electrical engineering.
Index Terms--Genre/Form:

554714
Electronic books.

Analog integrated circuit design techniques for high-speed signal processing in communications systems.
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020 $a 9780549416531
035 $a (MiAaPQ)AAI3296397
035 $a AAI3296397
040 $a MiAaPQ $b eng $c MiAaPQ
099 $a TUL $f hyy $c available through World Wide Web
100 1 $a Hernandez Garduno, David. $3 1184169
245 1 0 $a Analog integrated circuit design techniques for high-speed signal processing in communications systems.
264 0 $c 2006
300 $a 1 online resource (143 pages)
336 $a text $b txt $2 rdacontent
337 $a computer $b c $2 rdamedia
338 $a online resource $b cr $2 rdacarrier
500 $a Source: Dissertation Abstracts International, Volume: 69-01, Section: B, page: 5430.
500 $a Adviser: Jose Silva-Martinez.
502 $a Thesis (Ph.D.) $c Texas A&M University $d 2006.
504 $a Includes bibliographical references
520 $a This work presents design techniques for the implementation of high-speed analog integrated circuits for wireless and wireline communications systems.
520 $a Limitations commonly found in high-speed switched-capacitor (SC) circuits used for intermediate frequency (IF) filters in wireless receivers are explored. A model to analyze the aliasing effects due to periodical non-uniform individual sampling, a technique used in high-Q high-speed SC filters, is presented along with practical expressions that estimate the power of the generated alias components. The results are verified through circuit simulation of a 10.7MHz bandpass SC filter in TSMC 0.35mum CMOS technology. Implications on the use of this technique on the design of IF filters are discussed.
520 $a To improve the speed at which SC networks can operate, a continuous-time common-mode feedback (CMFB) with reduced loading capacitance is proposed. This increases the achievable gain-bandwidth product (GBW) of fully-differential ampliers. The performance of the CMFB is demonstrated in the implementation of a second-order 10.7MHz bandpass SC filter and compared with that of an identical filter using the conventional switched-capacitor CMFB (SC-CMFB). The filter using the continuous-time CMFB reduces the error due to finite GBW and slew rate to less than 1% for clock frequencies up to 72MHz while providing a dynamic range of 59dB and a PSRR- > 22dB.
520 $a The design of high-speed transversal equalizers for wireline transceivers requires the implementation of broadband delay lines. A delay line based on a third-order linear-phase filter is presented for the implementation of a fractionally-spaced 1Gb/s transversal equalizer. Two topologies for a broadband summing node which enable the placement of the parasitic poles at the output of the transversal equalizer beyond 650MHz are presented. Using these cells, a 5-tap 1Gb/s equalizer was implemented in TSMC 0.35mum CMOS technology. The results show a programmable frequency response able to compensate up to 25dB loss at 500MHz. The eye-pattern diagrams at 1Gb/s demonstrate the equalization of 15 meters and 23 meters of CAT5e twisted-pair cable, with a vertical eye-opening improvement from 0% (before the equalizer) to 58% (after the equalizer) in the second case. The equalizer consumes 96mW and an area of 630mum x 490mum.
533 $a Electronic reproduction. $b Ann Arbor, Mich. : $c ProQuest, $d 2018
538 $a Mode of access: World Wide Web
650 4 $a Electrical engineering. $3 596380
655 7 $a Electronic books. $2 local $3 554714
690 $a 0544
710 2 $a ProQuest Information and Learning Co. $3 1178819
710 2 $a Texas A&M University. $3 845439
773 0 $t Dissertation Abstracts International $g 69-01B.
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3296397 $z click for full text (PQDT)