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Very low power sigma delta modulator for WCDMA.

Record Type:	Language materials, manuscript : Monograph/item
Title/Author:	Very low power sigma delta modulator for WCDMA./
Author:	Bilhan, Erkan.
Description:	1 online resource (128 pages)
Notes:	Source: Dissertation Abstracts International, Volume: 69-12, Section: B, page: 7692.
Contained By:	Dissertation Abstracts International69-12B.
Subject:	Electrical engineering. -
Online resource:	click for full text (PQDT)
ISBN:	9780549951155

Very low power sigma delta modulator for WCDMA.
Bilhan, Erkan.

Very low power sigma delta modulator for WCDMA. - 1 online resource (128 pages)

Source: Dissertation Abstracts International, Volume: 69-12, Section: B, page: 7692.

Thesis (Ph.D.)

Includes bibliographical references

The ever growing portable semiconductor market demands high performance analog-to-digital converters (ADCs) in terms of resolution and signal bandwidth with stringent requirements on the power consumption, in order to maintain a longer battery life. The analog circuitries are required to be integrated with the digital circuitries to provide system-on-chip solutions (SOCs). This leads to a need for analog circuitries to be implemented in digital technologies where high performance and precision devices do not exist. For the portable applications sigma-delta ADCs are preferred due to their high performance in the absence of precision components and low power consumption. The resolution of a sigma-delta ADC can be increased by increasing one or more of the three parameters; number of bits used for the flash, over-sampling ratio (OSR), and the order of the modulator. The increase in the number of bits is limited due to the exponential increase in the area consumption as well as the complexity of the implementation of the digital-to-analog converter (DAC) in the feedback loop. OSR can be increased by increasing the sampling frequency; however, this increases the power consumption of the analog circuits. Higher order of modulators can be achieved by either cascading low order modulators or increasing the number of integration loops in single loop architectures. Beyond 2nd order, the single loop modulators exhibit stability problems. Due to this apparent trade-off, the system architecture and parameters have to be optimized to meet the desired system specifications. This research presents a new sigma-delta modulator architecture that utilizes 1st order, two-path, time-interleaved modulator to obtain a 2nd order noise shaping. The increase in the order of the modulator is achieved by cross-coupling of the quantization noise between two paths. The modulator architecture has the advantage of reducing the speed of the conversion by half, compared to traditional 2nd order modulators. Therefore, it enables low power implementations for low OSR, wide bandwidth applications. Furthermore, the proposed 2nd order modulator can be implemented with just one opamp. The reduction in active components enables further power savings. The sigma delta ADC is implemented and simulated using a 90nm CMOS technology.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2018

Mode of access: World Wide Web

ISBN: 9780549951155Subjects--Topical Terms:

596380
Electrical engineering.
Index Terms--Genre/Form:

554714
Electronic books.

Very low power sigma delta modulator for WCDMA.
LDR:03550ntm a2200325Ki 4500 001 912010
005 20180605073452.5
006 m o u
007 cr mn||||a|a||
008 190606s2008 xx obm 000 0 eng d
020 $a 9780549951155
035 $a (MiAaPQ)AAI3340466
035 $a AAI3340466
040 $a MiAaPQ $b eng $c MiAaPQ
099 $a TUL $f hyy $c available through World Wide Web
100 1 $a Bilhan, Erkan. $3 1184172
245 1 0 $a Very low power sigma delta modulator for WCDMA.
264 0 $c 2008
300 $a 1 online resource (128 pages)
336 $a text $b txt $2 rdacontent
337 $a computer $b c $2 rdamedia
338 $a online resource $b cr $2 rdacarrier
500 $a Source: Dissertation Abstracts International, Volume: 69-12, Section: B, page: 7692.
500 $a Advisers: Franco Maloberti; Jin Lui.
502 $a Thesis (Ph.D.) $c The University of Texas at Dallas $d 2008.
504 $a Includes bibliographical references
520 $a The ever growing portable semiconductor market demands high performance analog-to-digital converters (ADCs) in terms of resolution and signal bandwidth with stringent requirements on the power consumption, in order to maintain a longer battery life. The analog circuitries are required to be integrated with the digital circuitries to provide system-on-chip solutions (SOCs). This leads to a need for analog circuitries to be implemented in digital technologies where high performance and precision devices do not exist. For the portable applications sigma-delta ADCs are preferred due to their high performance in the absence of precision components and low power consumption. The resolution of a sigma-delta ADC can be increased by increasing one or more of the three parameters; number of bits used for the flash, over-sampling ratio (OSR), and the order of the modulator. The increase in the number of bits is limited due to the exponential increase in the area consumption as well as the complexity of the implementation of the digital-to-analog converter (DAC) in the feedback loop. OSR can be increased by increasing the sampling frequency; however, this increases the power consumption of the analog circuits. Higher order of modulators can be achieved by either cascading low order modulators or increasing the number of integration loops in single loop architectures. Beyond 2nd order, the single loop modulators exhibit stability problems. Due to this apparent trade-off, the system architecture and parameters have to be optimized to meet the desired system specifications. This research presents a new sigma-delta modulator architecture that utilizes 1st order, two-path, time-interleaved modulator to obtain a 2nd order noise shaping. The increase in the order of the modulator is achieved by cross-coupling of the quantization noise between two paths. The modulator architecture has the advantage of reducing the speed of the conversion by half, compared to traditional 2nd order modulators. Therefore, it enables low power implementations for low OSR, wide bandwidth applications. Furthermore, the proposed 2nd order modulator can be implemented with just one opamp. The reduction in active components enables further power savings. The sigma delta ADC is implemented and simulated using a 90nm CMOS technology.
533 $a Electronic reproduction. $b Ann Arbor, Mich. : $c ProQuest, $d 2018
538 $a Mode of access: World Wide Web
650 4 $a Electrical engineering. $3 596380
655 7 $a Electronic books. $2 local $3 554714
690 $a 0544
710 2 $a ProQuest Information and Learning Co. $3 1178819
710 2 $a The University of Texas at Dallas. $3 1184173
773 0 $t Dissertation Abstracts International $g 69-12B.
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3340466 $z click for full text (PQDT)