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Design techniques for high speed low voltage and low power non-calibrated pipeline analog to digital converters.

紀錄類型:	書目-語言資料,手稿 : Monograph/item
正題名/作者:	Design techniques for high speed low voltage and low power non-calibrated pipeline analog to digital converters./
作者:	Assaad, Rida Shawky.
面頁冊數:	1 online resource (239 pages)
附註:	Source: Dissertation Abstracts International, Volume: 71-03, Section: B, page: 1908.
Contained By:	Dissertation Abstracts International71-03B.
標題:	Electrical engineering. -
電子資源:	click for full text (PQDT)
ISBN:	9781109678086

Design techniques for high speed low voltage and low power non-calibrated pipeline analog to digital converters.
Assaad, Rida Shawky.

Design techniques for high speed low voltage and low power non-calibrated pipeline analog to digital converters. - 1 online resource (239 pages)

Source: Dissertation Abstracts International, Volume: 71-03, Section: B, page: 1908.

Thesis (Ph.D.)

Includes bibliographical references

This item is not available from ProQuest Dissertations & Theses.

The profound digitization of modern microelectronic modules made Analog-to Digital converters (ADC) key components in many systems. With resolutions up to 14bits and sampling rates in the 100s of MHz, the pipeline ADC is a prime candidate for a wide range of applications such as instrumentation, communications and consumer electronics. However, while past work focused on enhancing the performance of the pipeline ADC from an architectural standpoint, little has been done to individually address its fundamental building blocks. This work aims to achieve the latter by proposing design techniques to improve the performance of these blocks with minimal power consumption in low voltage environments, such that collectively high performance is achieved in the pipeline ADC.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2018

Mode of access: World Wide Web

ISBN: 9781109678086Subjects--Topical Terms:

596380
Electrical engineering.
Index Terms--Genre/Form:

554714
Electronic books.

Design techniques for high speed low voltage and low power non-calibrated pipeline analog to digital converters.
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245 1 0 $a Design techniques for high speed low voltage and low power non-calibrated pipeline analog to digital converters.
264 0 $c 2009
300 $a 1 online resource (239 pages)
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500 $a Source: Dissertation Abstracts International, Volume: 71-03, Section: B, page: 1908.
500 $a Adviser: Jose Silva-Martinez.
502 $a Thesis (Ph.D.) $c Texas A&M University $d 2009.
504 $a Includes bibliographical references
506 $a This item is not available from ProQuest Dissertations & Theses.
520 $a The profound digitization of modern microelectronic modules made Analog-to Digital converters (ADC) key components in many systems. With resolutions up to 14bits and sampling rates in the 100s of MHz, the pipeline ADC is a prime candidate for a wide range of applications such as instrumentation, communications and consumer electronics. However, while past work focused on enhancing the performance of the pipeline ADC from an architectural standpoint, little has been done to individually address its fundamental building blocks. This work aims to achieve the latter by proposing design techniques to improve the performance of these blocks with minimal power consumption in low voltage environments, such that collectively high performance is achieved in the pipeline ADC.
520 $a Towards this goal, a Recycling Folded Cascode (RFC) amplifier is proposed as an enhancement to the general performance of the conventional folded cascode. Tested in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18microm Complementary Metal Oxide Semiconductor (CMOS) technology, the RFC provides twice the bandwidth, 8--10dB additional gain, more than twice the slew rate and improved noise performance over the conventional folded cascode---all at no additional power or silicon area. The direct auto-zeroing offset cancellation scheme is optimized for low voltage environments using a dual level common mode feedback (CMFB) circuit, and amplifier differential offsets up to 50mV are effectively cancelled. Together with the RFC, the dual level CMFB was used to implement a sample and hold amplifier driving a single-ended load of 1.4pF and using only 2.6mA; at 200MS/s better than 9bit linearity is achieved. Finally a power conscious technique is proposed to reduce the kickback noise of dynamic comparators without resorting to the use of pre-amplifiers. When all techniques are collectively used to implement a 1Vpp 10bit 160MS/s pipeline ADC in Semiconductor Manufacturing International Corporation (SMIC) 0.18microm CMOS, 9.2 effective number of bits (ENOB) is achieved with a near Nyquist-rate full scale signal. The ADC uses an area of 1.1mm2 and consumes 42mW in its analog core. Compared to recent state-of-the-art implementations in the 100-200MS/s range, the presented pipeline ADC uses the least power per conversion rated at 0.45pJ/conversion-step.
533 $a Electronic reproduction. $b Ann Arbor, Mich. : $c ProQuest, $d 2018
538 $a Mode of access: World Wide Web
650 4 $a Electrical engineering. $3 596380
655 7 $a Electronic books. $2 local $3 554714
690 $a 0544
710 2 $a ProQuest Information and Learning Co. $3 1178819
710 2 $a Texas A&M University. $3 845439
773 0 $t Dissertation Abstracts International $g 71-03B.
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3400682 $z click for full text (PQDT)