國立虎尾科技大學 |

Calibrated continuous-time sigma -delta modulators.

紀錄類型:	書目-語言資料,手稿 : Monograph/item
正題名/作者:	Calibrated continuous-time sigma -delta modulators./
作者:	Lu, Cho-Ying.
面頁冊數:	1 online resource (175 pages)
附註:	Source: Dissertation Abstracts International, Volume: 71-08, Section: B, page: 5022.
Contained By:	Dissertation Abstracts International71-08B.
標題:	Electrical engineering. -
電子資源:	click for full text (PQDT)
ISBN:	9781124126975

Calibrated continuous-time sigma -delta modulators.
Lu, Cho-Ying.

Calibrated continuous-time sigma -delta modulators. - 1 online resource (175 pages)

Source: Dissertation Abstracts International, Volume: 71-08, Section: B, page: 5022.

Thesis (Ph.D.)

Includes bibliographical references

To provide more information mobility, many wireless communication systems such as WCDMA and EDGE in phone systems, bluetooth and WIMAX in communication networks have been recently developed. Recent efforts have been made to build the all-in-one next generation device which integrates a large number of wireless services into a single receiving path in order to raise the competitiveness of the device. Among all the receiver architectures, the high-IF receiver presents several unique properties for the next generation receiver by digitalizing the signal at the intermediate frequency around a few hundred MHz. In this architecture, the modulation/demodulation schemes, protocols, equalization, etc., are all determined in a software platform that runs in the digital signal processor (DSP) or FPGA. The specifications for most of front-end building blocks are relaxed, except the analog-to-digital converter (ADC). The requirements of large bandwidth, high operational frequency and high resolution make the design of the ADC very challenging.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2018

Mode of access: World Wide Web

ISBN: 9781124126975Subjects--Topical Terms:

596380
Electrical engineering.
Index Terms--Genre/Form:

554714
Electronic books.

Calibrated continuous-time sigma -delta modulators.
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100 1 $a Lu, Cho-Ying. $3 1184177
245 1 0 $a Calibrated continuous-time sigma -delta modulators.
264 0 $c 2010
300 $a 1 online resource (175 pages)
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500 $a Source: Dissertation Abstracts International, Volume: 71-08, Section: B, page: 5022.
500 $a Adviser: Jose Silva-Martinez.
502 $a Thesis (Ph.D.) $c Texas A&M University $d 2010.
504 $a Includes bibliographical references
520 $a To provide more information mobility, many wireless communication systems such as WCDMA and EDGE in phone systems, bluetooth and WIMAX in communication networks have been recently developed. Recent efforts have been made to build the all-in-one next generation device which integrates a large number of wireless services into a single receiving path in order to raise the competitiveness of the device. Among all the receiver architectures, the high-IF receiver presents several unique properties for the next generation receiver by digitalizing the signal at the intermediate frequency around a few hundred MHz. In this architecture, the modulation/demodulation schemes, protocols, equalization, etc., are all determined in a software platform that runs in the digital signal processor (DSP) or FPGA. The specifications for most of front-end building blocks are relaxed, except the analog-to-digital converter (ADC). The requirements of large bandwidth, high operational frequency and high resolution make the design of the ADC very challenging.
520 $a Solving the bottleneck associated with the high-IF receiver architecture is a major focus of many ongoing research efforts. In this work, a 6th-order bandpass continuous-time sigma-delta ADC with measured 68.4dB SNDR at 10MHz bandwidth to accommodate video applications is proposed. Tuned at 200 MHz, the fs/4 architecture employs an 800 MHz clock frequency. By making use of a unique software-based calibration scheme together with the tuning properties of the bandpass filters developed under the umbrella of this project, the ADC performance is optimized automatically to fulfill all requirements for the high-IF architecture.
520 $a In a separate project, other critical design issues for continuous-time sigma-delta ADCs are addressed, especially the issues related to unit current source mismatches in multi-level DACs as well as excess loop delays that may cause loop instability. The reported solutions are revisited to find more efficient architectures. The aforementioned techniques are used for the design of a 25MHz bandwidth lowpass continuous-time sigma-delta modulator with time-domain two-step 3-bit quantizer and DAC for WiMAX applications. The prototype is designed by employing a level-to-pulse-width modulation (PWM) converter followed by a single-level DAC in the feedback path to translate the typical digital codes into PWM signals with the proposed pulse arrangement. Therefore, the non-linearity issue from current source mismatch in multi-level DACs is prevented. The jitter behavior and timing mismatch issue of the proposed time-based methods are fully analyzed. The measurement results of a chip prototype achieving 67.7dB peak SNDR and 78dB SFDR in 25MHz bandwidth properly demonstrate the design concepts and effectiveness of time-based quantization and feedback.
520 $a Both continuous-time sigma-delta ADCs were fabricated in mainstream CMOS 0.18um technologies, which are the most popular in today's consumer electronics industry.
533 $a Electronic reproduction. $b Ann Arbor, Mich. : $c ProQuest, $d 2018
538 $a Mode of access: World Wide Web
650 4 $a Electrical engineering. $3 596380
655 7 $a Electronic books. $2 local $3 554714
690 $a 0544
710 2 $a ProQuest Information and Learning Co. $3 1178819
710 2 $a Texas A&M University. $3 845439
773 0 $t Dissertation Abstracts International $g 71-08B.
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3416243 $z click for full text (PQDT)