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Architectural Compensation Technique...
~
Maghari, Nima.
Architectural Compensation Techniques for Analog Inaccuracies in DeltaSigma Analog-to-Digital Converters.
紀錄類型:
書目-語言資料,手稿 : Monograph/item
正題名/作者:
Architectural Compensation Techniques for Analog Inaccuracies in DeltaSigma Analog-to-Digital Converters./
作者:
Maghari, Nima.
面頁冊數:
1 online resource (126 pages)
附註:
Source: Dissertation Abstracts International, Volume: 72-03, Section: B, page: 1680.
Contained By:
Dissertation Abstracts International72-03B.
標題:
Electrical engineering. -
電子資源:
click for full text (PQDT)
ISBN:
9781124463179
Architectural Compensation Techniques for Analog Inaccuracies in DeltaSigma Analog-to-Digital Converters.
Maghari, Nima.
Architectural Compensation Techniques for Analog Inaccuracies in DeltaSigma Analog-to-Digital Converters.
- 1 online resource (126 pages)
Source: Dissertation Abstracts International, Volume: 72-03, Section: B, page: 1680.
Thesis (Ph.D.)
Includes bibliographical references
Delta-sigma analog-to-digital converters (ADCs) are suitable for many applications due to several advantages such as relaxed anti-aliasing filter, high signal-to-noise and distortion ratio (SNDR) and most important of all, reduced sensitivity to analog imperfections. This thesis introduces several structures to overcome loop imperfections and stability issues in delta-sigma modulators. First, a new multi-loop delta-sigma modulator is proposed to combine the relaxed circuit requirements of single-loop modulators with the stability of traditional multi-loop modulators. Measurement results of the prototype IC confirmed with opamps with loop gain of less than 30dB, SNDR of over 74dB can be achieved. Also proposed is a new single-loop modulator using a delay-free two-step quantizer enabling the input signals beyond the full-scale range to be processed by the loop. The fabricated prototype IC achieves over 75dB SNDR by allowing signals up to +5dBFS input signals. Third, is a modified dual-slope ADC which achieves first-order quantization noise-shaping. Combined as the quantizer of a second-order delta-sigma loop, the fabricated prototype IC achieves third-order noise shaping with 78dB peak SNDR.
Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2018
Mode of access: World Wide Web
ISBN: 9781124463179Subjects--Topical Terms:
596380
Electrical engineering.
Index Terms--Genre/Form:
554714
Electronic books.
Architectural Compensation Techniques for Analog Inaccuracies in DeltaSigma Analog-to-Digital Converters.
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click for full text (PQDT)
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