語系:
繁體中文
English
說明(常見問題)
登入
回首頁
切換:
標籤
|
MARC模式
|
ISBD
Design of Low OSR, High Precision An...
~
ProQuest Information and Learning Co.
Design of Low OSR, High Precision Analog-to-Digital Converters.
紀錄類型:
書目-語言資料,手稿 : Monograph/item
正題名/作者:
Design of Low OSR, High Precision Analog-to-Digital Converters./
作者:
Rajaee, Omid.
面頁冊數:
1 online resource (131 pages)
附註:
Source: Dissertation Abstracts International, Volume: 72-06, Section: B, page: 3633.
Contained By:
Dissertation Abstracts International72-06B.
標題:
Electrical engineering. -
電子資源:
click for full text (PQDT)
ISBN:
9781124596099
Design of Low OSR, High Precision Analog-to-Digital Converters.
Rajaee, Omid.
Design of Low OSR, High Precision Analog-to-Digital Converters.
- 1 online resource (131 pages)
Source: Dissertation Abstracts International, Volume: 72-06, Section: B, page: 3633.
Thesis (Ph.D.)
Includes bibliographical references
This item is not available from ProQuest Dissertations & Theses.
Advances in electronic systems have lead to the demand for high resolution, high bandwidth Analog-to-Digital Converters (ADCs). Oversampled ADCs are well-known for high accuracy applications since they benefit from noise shaping and they usually do not need highly accurate components. However, as a consequence of oversampling, they have limited signal bandwidth. The signal bandwidth (BW) of oversampled ADCs can be increased either by increasing the sampling rate or reducing the oversampling ratio (OSR). Reducing OSR is a more promising method for increasing the BW, since the sampling speed is usually limited by the technology. The advantageous properties (e.g. low in-band quantization, relaxed accuracy requirements of components) of oversampled ADCs are usually diminished at lower OSRs and preserving these properties requires complicated and power hungry architectures.
Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2018
Mode of access: World Wide Web
ISBN: 9781124596099Subjects--Topical Terms:
596380
Electrical engineering.
Index Terms--Genre/Form:
554714
Electronic books.
Design of Low OSR, High Precision Analog-to-Digital Converters.
LDR
:02963ntm a2200349Ki 4500
001
912018
005
20180605073452.5
006
m o u
007
cr mn||||a|a||
008
190606s2010 xx obm 000 0 eng d
020
$a
9781124596099
035
$a
(MiAaPQ)AAI3452574
035
$a
AAI3452574
040
$a
MiAaPQ
$b
eng
$c
MiAaPQ
099
$a
TUL
$f
hyy
$c
available through World Wide Web
100
1
$a
Rajaee, Omid.
$3
1184182
245
1 0
$a
Design of Low OSR, High Precision Analog-to-Digital Converters.
264
0
$c
2010
300
$a
1 online resource (131 pages)
336
$a
text
$b
txt
$2
rdacontent
337
$a
computer
$b
c
$2
rdamedia
338
$a
online resource
$b
cr
$2
rdacarrier
500
$a
Source: Dissertation Abstracts International, Volume: 72-06, Section: B, page: 3633.
500
$a
Adviser: Un-Ku Moon.
502
$a
Thesis (Ph.D.)
$c
Oregon State University
$d
2010.
504
$a
Includes bibliographical references
506
$a
This item is not available from ProQuest Dissertations & Theses.
520
$a
Advances in electronic systems have lead to the demand for high resolution, high bandwidth Analog-to-Digital Converters (ADCs). Oversampled ADCs are well-known for high accuracy applications since they benefit from noise shaping and they usually do not need highly accurate components. However, as a consequence of oversampling, they have limited signal bandwidth. The signal bandwidth (BW) of oversampled ADCs can be increased either by increasing the sampling rate or reducing the oversampling ratio (OSR). Reducing OSR is a more promising method for increasing the BW, since the sampling speed is usually limited by the technology. The advantageous properties (e.g. low in-band quantization, relaxed accuracy requirements of components) of oversampled ADCs are usually diminished at lower OSRs and preserving these properties requires complicated and power hungry architectures.
520
$a
In this thesis, different combinations of delta-sigma and pipelined ADCs are explored and new techniques for designing oversampled ADCs are proposed. A Hybrid Delta-Sigma/Pipelined (HDSP) ADC is presented. This ADC uses a pipelined ADC as the quantizer of a single-loop delta-sigma modulator and benefits from the aggressive quantization of the pipelined quantizer at low OSRs. A Noise-Shaped Pipelined ADC is proposed which exploits a delta-sigma modulator as the sub-ADC of a pipeline stage to reduce the sensitivity to the analog imperfection. Three prototype ADCs were fabricated in 0.18microm CMOS technology to verify the effectiveness of the proposed techniques. The performance of these architectures is among the best reported for high bandwidth oversampled ADCs.
533
$a
Electronic reproduction.
$b
Ann Arbor, Mich. :
$c
ProQuest,
$d
2018
538
$a
Mode of access: World Wide Web
650
4
$a
Electrical engineering.
$3
596380
655
7
$a
Electronic books.
$2
local
$3
554714
690
$a
0544
710
2
$a
ProQuest Information and Learning Co.
$3
1178819
710
2
$a
Oregon State University.
$3
560908
773
0
$t
Dissertation Abstracts International
$g
72-06B.
856
4 0
$u
http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3452574
$z
click for full text (PQDT)
筆 0 讀者評論
多媒體
評論
新增評論
分享你的心得
Export
取書館別
處理中
...
變更密碼[密碼必須為2種組合(英文和數字)及長度為10碼以上]
登入