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Power-Efficient Two-Step Pipelined A...
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ProQuest Information and Learning Co.
Power-Efficient Two-Step Pipelined Analog-to-Digital Conversion.
紀錄類型:
書目-語言資料,手稿 : Monograph/item
正題名/作者:
Power-Efficient Two-Step Pipelined Analog-to-Digital Conversion./
作者:
Lee, Ho-Young.
面頁冊數:
1 online resource (126 pages)
附註:
Source: Dissertation Abstracts International, Volume: 73-05, Section: B, page: 3147.
Contained By:
Dissertation Abstracts International73-05B.
標題:
Electrical engineering. -
電子資源:
click for full text (PQDT)
ISBN:
9781267136589
Power-Efficient Two-Step Pipelined Analog-to-Digital Conversion.
Lee, Ho-Young.
Power-Efficient Two-Step Pipelined Analog-to-Digital Conversion.
- 1 online resource (126 pages)
Source: Dissertation Abstracts International, Volume: 73-05, Section: B, page: 3147.
Thesis (Ph.D.)
Includes bibliographical references
This item is not available from ProQuest Dissertations & Theses.
Hand-held devices are among the most successful consumer electronics in modern society. Behind these successful devices, lies a key analog design technique that involves high-performance analog-to-digital conversion combined with very low power consumption. This dissertation presents two different approaches to achieving high power efficiency from a two-step pipelined architecture, which is generally known as one of the most power-consuming analog-to-digital converters.
Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2018
Mode of access: World Wide Web
ISBN: 9781267136589Subjects--Topical Terms:
596380
Electrical engineering.
Index Terms--Genre/Form:
554714
Electronic books.
Power-Efficient Two-Step Pipelined Analog-to-Digital Conversion.
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Includes bibliographical references
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This item is not available from ProQuest Dissertations & Theses.
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Hand-held devices are among the most successful consumer electronics in modern society. Behind these successful devices, lies a key analog design technique that involves high-performance analog-to-digital conversion combined with very low power consumption. This dissertation presents two different approaches to achieving high power efficiency from a two-step pipelined architecture, which is generally known as one of the most power-consuming analog-to-digital converters.
520
$a
In the first approach, an analog feedback loop of a residue amplifier in a two-step pipelined analog-to-digital converter is reconfigured digitally using a single comparator and an R-2R digital-to-analog converter. This comparator-based structure can reduce power consumption of a conventional two-step pipelined analog-to-digital converter which consists of an opamp-based residue amplifier followed by a second-stage analog-to-digital converter. In addition, this dissertation includes circuit design techniques that provide a digital offset correction for the comparator-based two-step structure, binary-weighted switching for an R-2R digital-to-analog converter, and reference trimming for a flash analog-to-digital converter. A 10-b prototype analog-to-digital converter achieves an FOM of 121 fJ/conversion-step under 0.7-V supply.
520
$a
The second approach provides a way to achieve low power consumption for a high-resolution two-step pipelined analog-to-digital converter. An opamp is designed to consume optimized static power using a quarter-scaled residue gain together with minimized loading capacitance from the proposed second stage. A 14-b prototype analog-to-digital converter achieves an FOM of 31.3 fJ/conversion-step with an ENOB of 11.4 b, which is the lowest FOM in high-resolution analog-to-digital converters having greater than an ENOB of 10 b.
520
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Finally, the potential for further power reduction in a two-step pipelined analog-to-digital converter is discussed as a topic for future research.
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Ann Arbor, Mich. :
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ProQuest,
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2018
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