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SHA-less pipeline ADC design with sampling clock skew calibration.

Record Type:	Language materials, manuscript : Monograph/item
Title/Author:	SHA-less pipeline ADC design with sampling clock skew calibration./
Author:	Huang, Pingli.
Description:	1 online resource (136 pages)
Notes:	Source: Dissertation Abstracts International, Volume: 73-08(E), Section: B.
Contained By:	Dissertation Abstracts International73-08B(E).
Subject:	Electrical engineering. -
Online resource:	click for full text (PQDT)
ISBN:	9781267272232

SHA-less pipeline ADC design with sampling clock skew calibration.
Huang, Pingli.

SHA-less pipeline ADC design with sampling clock skew calibration. - 1 online resource (136 pages)

Source: Dissertation Abstracts International, Volume: 73-08(E), Section: B.

Thesis (Ph.D.)

Includes bibliographical references

This item is not available from ProQuest Dissertations & Theses.

The power efficiency of pipeline analog-to-digital converters (ADCs) can be substantially improved by eliminating the front-end sample-and-hold amplifier (SHA). However, in a SHA-less architecture the sampling clock skew between the sub-ADC and the multiplying digital-to-analog converter (MDAC) in the pipeline first stage results in gross conversion errors at high input frequencies. This skew effect is aggravated in a SHA-less multi-bit-per-stage pipeline architecture, where the built-in redundancy is limited. Sampling clock skew is an essential problem in SHA-less pipeline ADCs that prohibits their use at high input frequency applications.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2018

Mode of access: World Wide Web

ISBN: 9781267272232Subjects--Topical Terms:

596380
Electrical engineering.
Index Terms--Genre/Form:

554714
Electronic books.

SHA-less pipeline ADC design with sampling clock skew calibration.
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099 $a TUL $f hyy $c available through World Wide Web
100 1 $a Huang, Pingli. $3 1184187
245 1 0 $a SHA-less pipeline ADC design with sampling clock skew calibration.
264 0 $c 2011
300 $a 1 online resource (136 pages)
336 $a text $b txt $2 rdacontent
337 $a computer $b c $2 rdamedia
338 $a online resource $b cr $2 rdacarrier
500 $a Source: Dissertation Abstracts International, Volume: 73-08(E), Section: B.
500 $a Adviser: Yun Chiu.
502 $a Thesis (Ph.D.) $c University of Illinois at Urbana-Champaign $d 2011.
504 $a Includes bibliographical references
506 $a This item is not available from ProQuest Dissertations & Theses.
520 $a The power efficiency of pipeline analog-to-digital converters (ADCs) can be substantially improved by eliminating the front-end sample-and-hold amplifier (SHA). However, in a SHA-less architecture the sampling clock skew between the sub-ADC and the multiplying digital-to-analog converter (MDAC) in the pipeline first stage results in gross conversion errors at high input frequencies. This skew effect is aggravated in a SHA-less multi-bit-per-stage pipeline architecture, where the built-in redundancy is limited. Sampling clock skew is an essential problem in SHA-less pipeline ADCs that prohibits their use at high input frequency applications.
520 $a In this thesis, a mostly digital background calibration technique is developed to remove the sampling clock skew in SHA-less pipeline ADCs. The skew information is extracted from the first-stage residue output with two comparators sensing out-of-range errors; a gradient-descent algorithm is used to adaptively adjust the timing of the sub-ADC to synchronize with that of the sample-and-hold (S/H) in the MDAC. A prototype 10-bit, 100-MS/s SHA-less pipeline ADC incorporating this calibration technique was designed and fabricated in 90-nm CMOS process. The prototype ADC converts from DC to the 12th Nyquist band with a 3.5-bit front-end stage. It digitizes inputs up to 610 MHz without skew errors in experiments; in contrast, the same ADC fails at 130 MHz with calibration disabled. The calibration circuits were fully integrated on chip. The ADC consumes 12.2 mW and occupies 0.26-mm2 silicon area, while the calibration circuits dissipate 0.9 mW and occupy 0.01 mm2. A 71-dB spurious-free dynamic range (SFDR) and a 55-dB signal-to-noise-and-distortion ratio (SNDR) were measured with a 20-MHz sine-wave input, and a larger than 55-dB SFDR was measured in the 10th Nyquist band.
533 $a Electronic reproduction. $b Ann Arbor, Mich. : $c ProQuest, $d 2018
538 $a Mode of access: World Wide Web
650 4 $a Electrical engineering. $3 596380
655 7 $a Electronic books. $2 local $3 554714
690 $a 0544
710 2 $a ProQuest Information and Learning Co. $3 1178819
710 2 $a University of Illinois at Urbana-Champaign. $b Electrical & Computer Eng. $3 1184123
773 0 $t Dissertation Abstracts International $g 73-08B(E).
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3503558 $z click for full text (PQDT)