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Triple Sampling an Application to a ...
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ProQuest Information and Learning Co.
Triple Sampling an Application to a 14b 10MS/s Cyclic ADC.
紀錄類型:
書目-語言資料,手稿 : Monograph/item
正題名/作者:
Triple Sampling an Application to a 14b 10MS/s Cyclic ADC./
作者:
Sivakumar, Balasubramanian.
面頁冊數:
1 online resource (117 pages)
附註:
Source: Dissertation Abstracts International, Volume: 74-04(E), Section: B.
Contained By:
Dissertation Abstracts International74-04B(E).
標題:
Electrical engineering. -
電子資源:
click for full text (PQDT)
ISBN:
9781267787200
Triple Sampling an Application to a 14b 10MS/s Cyclic ADC.
Sivakumar, Balasubramanian.
Triple Sampling an Application to a 14b 10MS/s Cyclic ADC.
- 1 online resource (117 pages)
Source: Dissertation Abstracts International, Volume: 74-04(E), Section: B.
Thesis (Ph.D.)
Includes bibliographical references
Semiconductor device scaling has kept up with Moore's law for the past decades and they have been scaling by a factor of half every one and half years. Every new generation of device technology opens up new opportunities and challenges and especially so for analog design. High speed and low gain is characteristic of these processes and hence a tradeoff that can enable to get back gain by trading speed is crucial. This thesis proposes a solution that increases the speed of sampling of a circuit by a factor of three while reducing the specifications on analog blocks and keeping the power nearly constant. The techniques are based on the switched capacitor technique called Correlated Level Shifting. A triple channel Cyclic ADC has been implemented, with each channel working at a sampling frequency of 3.33MS/s and a resolution of 14 bits. The specifications are compared with that based on a traditional architecture to show the superiority of the proposed technique.
Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2018
Mode of access: World Wide Web
ISBN: 9781267787200Subjects--Topical Terms:
596380
Electrical engineering.
Index Terms--Genre/Form:
554714
Electronic books.
Triple Sampling an Application to a 14b 10MS/s Cyclic ADC.
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Semiconductor device scaling has kept up with Moore's law for the past decades and they have been scaling by a factor of half every one and half years. Every new generation of device technology opens up new opportunities and challenges and especially so for analog design. High speed and low gain is characteristic of these processes and hence a tradeoff that can enable to get back gain by trading speed is crucial. This thesis proposes a solution that increases the speed of sampling of a circuit by a factor of three while reducing the specifications on analog blocks and keeping the power nearly constant. The techniques are based on the switched capacitor technique called Correlated Level Shifting. A triple channel Cyclic ADC has been implemented, with each channel working at a sampling frequency of 3.33MS/s and a resolution of 14 bits. The specifications are compared with that based on a traditional architecture to show the superiority of the proposed technique.
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click for full text (PQDT)
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