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A Low-Power High-Speed High-Resolution Zero-Crossing Based Pipelined Analog to Digital Converter.

Record Type:	Language materials, manuscript : Monograph/item
Title/Author:	A Low-Power High-Speed High-Resolution Zero-Crossing Based Pipelined Analog to Digital Converter./
Author:	Shin, Soonkyun.
Description:	1 online resource (144 pages)
Notes:	Source: Dissertation Abstracts International, Volume: 75-12(E), Section: B.
Contained By:	Dissertation Abstracts International75-12B(E).
Subject:	Electrical engineering. -
Online resource:	click for full text (PQDT)
ISBN:	9781321111361

A Low-Power High-Speed High-Resolution Zero-Crossing Based Pipelined Analog to Digital Converter.
Shin, Soonkyun.

A Low-Power High-Speed High-Resolution Zero-Crossing Based Pipelined Analog to Digital Converter. - 1 online resource (144 pages)

Source: Dissertation Abstracts International, Volume: 75-12(E), Section: B.

Thesis (Ph.D.)

Includes bibliographical references

This item is not available from ProQuest Dissertations & Theses.

In this dissertation, techniques with zero-crossing based circuits (ZCBC) to achieve high speed and high resolution in scaled technologies with very low intrinsic gain are proposed. A coarse phase followed by a level shifting capacitor for a fine phase current source is employed to achieve higher accuracy and sub-ADC flash comparators are strobed immediately after the coarse phase for high frequency operation. The systematic offset voltage between the coarse and fine phases manifests itself as systematic offset in the sub-ADC comparators. This offset is caused by the coarse phase undershoot and the fine phase overshoot. It is cancelled with background calibration by residue range correction circuits within the following stage's sub-ADC. The sub-ADC's random comparator offset is calibrated with a discrete-time charge-pump based background calibration technique. A prototype device based on the aforementioned concepts was realized in a 55nm CMOS process. The ADC occupies 0.282 mm2 and dissipates 30.7mW. It achieves 64.6dB SNDR and 82.9 dBc SFDR at 200 MS/s for a FOM of 111 fJ/conversion-step. The SNDR degrades gracefully above the designed sampling frequency to 62.9 dB at 250 MS/s, and remains above 50 dB at 300 MS/s. To minimize the power consumption further when using the ZCD technique, a dynamic biasing technique is proposed and employed. The bias current feeding the ZCD preamplifier is dynamic and depends on input ramp voltage. This method reduces current consumption by supplying bias current only when needed during a zero crossing event. This ADC consumes 27.1mW and achieved 61.2 dB SNDR for a FOM of 143 fJ/step.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2018

Mode of access: World Wide Web

ISBN: 9781321111361Subjects--Topical Terms:

596380
Electrical engineering.
Index Terms--Genre/Form:

554714
Electronic books.

A Low-Power High-Speed High-Resolution Zero-Crossing Based Pipelined Analog to Digital Converter.
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500 $a Source: Dissertation Abstracts International, Volume: 75-12(E), Section: B.
500 $a Adviser: Jacques C. Rudell.
502 $a Thesis (Ph.D.) $c University of Washington $d 2014.
504 $a Includes bibliographical references
506 $a This item is not available from ProQuest Dissertations & Theses.
520 $a In this dissertation, techniques with zero-crossing based circuits (ZCBC) to achieve high speed and high resolution in scaled technologies with very low intrinsic gain are proposed. A coarse phase followed by a level shifting capacitor for a fine phase current source is employed to achieve higher accuracy and sub-ADC flash comparators are strobed immediately after the coarse phase for high frequency operation. The systematic offset voltage between the coarse and fine phases manifests itself as systematic offset in the sub-ADC comparators. This offset is caused by the coarse phase undershoot and the fine phase overshoot. It is cancelled with background calibration by residue range correction circuits within the following stage's sub-ADC. The sub-ADC's random comparator offset is calibrated with a discrete-time charge-pump based background calibration technique. A prototype device based on the aforementioned concepts was realized in a 55nm CMOS process. The ADC occupies 0.282 mm2 and dissipates 30.7mW. It achieves 64.6dB SNDR and 82.9 dBc SFDR at 200 MS/s for a FOM of 111 fJ/conversion-step. The SNDR degrades gracefully above the designed sampling frequency to 62.9 dB at 250 MS/s, and remains above 50 dB at 300 MS/s. To minimize the power consumption further when using the ZCD technique, a dynamic biasing technique is proposed and employed. The bias current feeding the ZCD preamplifier is dynamic and depends on input ramp voltage. This method reduces current consumption by supplying bias current only when needed during a zero crossing event. This ADC consumes 27.1mW and achieved 61.2 dB SNDR for a FOM of 143 fJ/step.
533 $a Electronic reproduction. $b Ann Arbor, Mich. : $c ProQuest, $d 2018
538 $a Mode of access: World Wide Web
650 4 $a Electrical engineering. $3 596380
655 7 $a Electronic books. $2 local $3 554714
690 $a 0544
710 2 $a ProQuest Information and Learning Co. $3 1178819
710 2 $a University of Washington. $b Electrical Engineering. $3 1180628
773 0 $t Dissertation Abstracts International $g 75-12B(E).
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