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Clock generation design for continuo...
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ProQuest Information and Learning Co.
Clock generation design for continuous-time sigma-delta analog-to-digital converter in communication systems.
紀錄類型:
書目-語言資料,手稿 : Monograph/item
正題名/作者:
Clock generation design for continuous-time sigma-delta analog-to-digital converter in communication systems./
作者:
Lo, Yung-Chung.
面頁冊數:
1 online resource (166 pages)
附註:
Source: Dissertation Abstracts International, Volume: 77-01(E), Section: B.
Contained By:
Dissertation Abstracts International77-01B(E).
標題:
Electrical engineering. -
電子資源:
click for full text (PQDT)
ISBN:
9781321973495
Clock generation design for continuous-time sigma-delta analog-to-digital converter in communication systems.
Lo, Yung-Chung.
Clock generation design for continuous-time sigma-delta analog-to-digital converter in communication systems.
- 1 online resource (166 pages)
Source: Dissertation Abstracts International, Volume: 77-01(E), Section: B.
Thesis (Ph.D.)
Includes bibliographical references
This item is not available from ProQuest Dissertations & Theses.
Software defined radio, a highly digitized wireless receiver, has drawn huge attention in modern communication system because it can not only benefit from the advanced technologies but also exploit large digital calibration of digital signal processing (DSP) to optimize the performance of receivers. Continuous-time (CT) bandpass sigma-delta (SigmaDelta) modulator, used as an RF-to-digital converter, has been regarded as a potential solution for software defined ratio. The demand to support multiple standards motivates the development of a broadband CT bandpass SigmaDelta which can cover the most commercial spectrum of 1GHz to 4GHz in a modern communication system.
Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2018
Mode of access: World Wide Web
ISBN: 9781321973495Subjects--Topical Terms:
596380
Electrical engineering.
Index Terms--Genre/Form:
554714
Electronic books.
Clock generation design for continuous-time sigma-delta analog-to-digital converter in communication systems.
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Clock generation design for continuous-time sigma-delta analog-to-digital converter in communication systems.
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Source: Dissertation Abstracts International, Volume: 77-01(E), Section: B.
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Adviser: Jose Silva-Martinez.
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Thesis (Ph.D.)
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Texas A&M University
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2014.
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Includes bibliographical references
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This item is not available from ProQuest Dissertations & Theses.
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Software defined radio, a highly digitized wireless receiver, has drawn huge attention in modern communication system because it can not only benefit from the advanced technologies but also exploit large digital calibration of digital signal processing (DSP) to optimize the performance of receivers. Continuous-time (CT) bandpass sigma-delta (SigmaDelta) modulator, used as an RF-to-digital converter, has been regarded as a potential solution for software defined ratio. The demand to support multiple standards motivates the development of a broadband CT bandpass SigmaDelta which can cover the most commercial spectrum of 1GHz to 4GHz in a modern communication system.
520
$a
Clock generation, a major building block in radio frequency (RF) integrated circuits (ICs), usually uses a phase-locked loop (PLL) to provide the required clock frequency to modulate/demodulate the informative signals. This work explores the design of clock generation in RF ICs. First, a 2-16 GHz frequency synthesizer is proposed to provide the sampling clocks for a programmable continuous-time bandpass sigma-delta (SigmaDelta) modulator in a software radio receiver system. In the frequency synthesizer, a single-sideband mixer combines feed-forward and regenerative mixing techniques to achieve the wide frequency range. Furthermore, to optimize the excess loop delay in the wideband system, a phase-tunable clock distribution network and a clock-controlled quantizer are proposed. Also, the false locking of regenerative mixing is solved by controlling the self-oscillation frequency of the CML divider. The proposed frequency synthesizer performs excellent jitter performance and efficient power consumption.
520
$a
Phase noise and quadrature phase accuracy are the common tradeoff in a quadrature voltage-controlled oscillator. A larger coupling ratio is preferred to obtain good phase accuracy but suffer phase noise performance. To address these fundamental trade-offs, a phasor-based analysis is used to explain bi-modal oscillation and compute the quadrature phase errors given by inevitable mismatches of components. Also, the ISF is used to estimate the noise contribution of each major noise source. A CSD QVCO is first proposed to eliminate the undesired bi-modal oscillation and enhance the quadrature phase accuracy. The second work presents a DCC QVCO. The sophisticated dynamic current-clipping coupling network reduces injecting noise into LC tank at most vulnerable timings (zero crossing points). Hence, it allows the use of strong coupling ratio to minimize the quadrature phase sensitivity to mismatches without degrading the phase noise performance. The proposed DCC QVCO is implemented in a 130-nm CMOS technology. The measured phase noise is -121 dBc/Hz at 1MHz offset from a 5GHz carrier. The QVCO consumes 4.2mW with a 1-V power supply, resulting in an outstanding Figure of Merit (FoM) of 189 dBc/Hz.
520
$a
Frequency divider is one of the most power hungry building blocks in a PLL-based frequency synthesizer. The complementary injection-locked frequency divider is proposed to be a low-power solution. With the complimentary injection schemes, the dividers can realize both even and odd division modulus, performing a more than 100% locking range to overcome the PVT variation. The proposed dividers feature excellent phase noise. They can be used for multiple-phase generation, programmable phase-switching frequency dividers, and phase-skewing circuits.
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Electronic reproduction.
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Ann Arbor, Mich. :
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ProQuest,
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2018
538
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Mode of access: World Wide Web
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Electrical engineering.
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596380
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Electronic books.
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690
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ProQuest Information and Learning Co.
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710
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Texas A&M University.
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Electrical and Computer Engineering.
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1184130
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Dissertation Abstracts International
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77-01B(E).
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http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3717779
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click for full text (PQDT)
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