國立虎尾科技大學 |

Low-Density Parity-Check Decoder Architectures for Integrated Circuits and Quantum Cryptography.

紀錄類型:	書目-語言資料,手稿 : Monograph/item
正題名/作者:	Low-Density Parity-Check Decoder Architectures for Integrated Circuits and Quantum Cryptography./
作者:	Milicevic, Mario.
面頁冊數:	1 online resource (127 pages)
附註:	Source: Dissertation Abstracts International, Volume: 79-04(E), Section: B.
標題:	Electrical engineering. -
電子資源:	click for full text (PQDT)
ISBN:	9780355530193

Low-Density Parity-Check Decoder Architectures for Integrated Circuits and Quantum Cryptography.
Milicevic, Mario.

Low-Density Parity-Check Decoder Architectures for Integrated Circuits and Quantum Cryptography. - 1 online resource (127 pages)

Source: Dissertation Abstracts International, Volume: 79-04(E), Section: B.

Thesis (Ph.D.)--University of Toronto (Canada), 2017.

Includes bibliographical references

Forward error correction enables reliable one-way communication over noisy channels, by transmitting redundant data along with the message in order to detect and resolve errors at the receiver. Low-density parity-check (LDPC) codes achieve superior error-correction performance on Gaussian channels under belief propagation decoding, however, their complex parity-check matrix structure introduces hardware implementation challenges. This thesis explores how the quasi-cyclic structure of LDPC parity-check matrices can be exploited in the design of low-power hardware architectures for multi-Gigabit/second decoders realized in CMOS technology, as well as in the design and construction of multi-edge LDPC codes for long-distance (beyond 100km) quantum cryptography over optical fiber.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2018

Mode of access: World Wide Web

ISBN: 9780355530193Subjects--Topical Terms:

596380
Electrical engineering.
Index Terms--Genre/Form:

554714
Electronic books.

Low-Density Parity-Check Decoder Architectures for Integrated Circuits and Quantum Cryptography.
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500 $a Source: Dissertation Abstracts International, Volume: 79-04(E), Section: B.
500 $a Adviser: Patrick G. Gulak.
502 $a Thesis (Ph.D.)--University of Toronto (Canada), 2017.
504 $a Includes bibliographical references
520 $a Forward error correction enables reliable one-way communication over noisy channels, by transmitting redundant data along with the message in order to detect and resolve errors at the receiver. Low-density parity-check (LDPC) codes achieve superior error-correction performance on Gaussian channels under belief propagation decoding, however, their complex parity-check matrix structure introduces hardware implementation challenges. This thesis explores how the quasi-cyclic structure of LDPC parity-check matrices can be exploited in the design of low-power hardware architectures for multi-Gigabit/second decoders realized in CMOS technology, as well as in the design and construction of multi-edge LDPC codes for long-distance (beyond 100km) quantum cryptography over optical fiber.
520 $a A frame-interleaved architecture is presented with a path-unrolled message-passing schedule to reduce the complexity of routing interconnect in an integrated circuit decoder implementation. A proof-of-concept silicon test chip was fabricated in the 28nm CMOS technology node. The LDPC decoder chip supports the four codes presented in the IEEE 802.11ad standard, occupies an area of 3.41mm 2, and achieves an energy efficiency of 15pJ/bit while delivering a maximum throughput of 6.78Gb/s, and operating with a 202MHz clock at 0.9V supply. The test chip achieves the highest normalized energy efficiency among published CMOS-based decoders for the IEEE 802.11ad standard.
520 $a A quasi-cyclic code construction technique is applied to a multi-edge LDPC code with block length of 106 bits in order to reduce the latency of LDPC decoding in the key reconciliation step of long-distance quantum key distribution. The GPU-based decoder achieves a maximum information throughput of 7.16Kb/s, and extends the current maximum transmission distance from 100km to 160km with a secret key rate of 4.10 x 10-7 bits/pulse under 8-dimensional reconciliation. The GPU-based decoder delivers up to 8.03x higher decoded information throughput over the upper bound on secret key rate for a lossy optical channel, thus demonstrating that key reconciliation with LDPC codes is no longer a post-processing bottleneck in quantum key distribution.
520 $a The contributions presented in this thesis can be applied to future research in the implementation of silicon-based linear-program decoders for high-reliability channels, and single-chip solutions for quantum key distribution containing integrated photonics and post-processing algorithms.
533 $a Electronic reproduction. $b Ann Arbor, Mich. : $c ProQuest, $d 2018
538 $a Mode of access: World Wide Web
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655 7 $a Electronic books. $2 local $3 554714
690 $a 0544
710 2 $a ProQuest Information and Learning Co. $3 1178819
710 2 $a University of Toronto (Canada). $b Electrical and Computer Engineering. $3 1148628
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