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Efficient Architectures for High Spe...

ProQuest Information and Learning Co.

Efficient Architectures for High Speed Binary Multipliers.

紀錄類型:	書目-語言資料,手稿 : Monograph/item
正題名/作者:	Efficient Architectures for High Speed Binary Multipliers./
作者:	Fritz, Christopher.
面頁冊數:	1 online resource (136 pages)
附註:	Source: Dissertation Abstracts International, Volume: 78-11(E), Section: B.
標題:	Electrical engineering. -
電子資源:	click for full text (PQDT)
ISBN:	9780355047226

Efficient Architectures for High Speed Binary Multipliers.
Fritz, Christopher.

Efficient Architectures for High Speed Binary Multipliers. - 1 online resource (136 pages)

Source: Dissertation Abstracts International, Volume: 78-11(E), Section: B.

Thesis (Ph.D.)--State University of New York at Buffalo, 2017.

Includes bibliographical references

Fast, efficient multiplication of binary operands in digital systems is a problem of critical importance to modern computing architectures. The efficiency of multiplier designs depends on the addition of partial products, and many methods of compressing partial products have been presented. These methods involve compressing bits of equal weight in iterative phases until two numbers remain to be added with a conventional adder circuit.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2018

Mode of access: World Wide Web

ISBN: 9780355047226Subjects--Topical Terms:

596380
Electrical engineering.
Index Terms--Genre/Form:

554714
Electronic books.

Efficient Architectures for High Speed Binary Multipliers.
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100 1 $a Fritz, Christopher. $3 1186962
245 1 0 $a Efficient Architectures for High Speed Binary Multipliers.
264 0 $c 2017
300 $a 1 online resource (136 pages)
336 $a text $b txt $2 rdacontent
337 $a computer $b c $2 rdamedia
338 $a online resource $b cr $2 rdacarrier
500 $a Source: Dissertation Abstracts International, Volume: 78-11(E), Section: B.
500 $a Adviser: Adly T. Fam.
502 $a Thesis (Ph.D.)--State University of New York at Buffalo, 2017.
504 $a Includes bibliographical references
520 $a Fast, efficient multiplication of binary operands in digital systems is a problem of critical importance to modern computing architectures. The efficiency of multiplier designs depends on the addition of partial products, and many methods of compressing partial products have been presented. These methods involve compressing bits of equal weight in iterative phases until two numbers remain to be added with a conventional adder circuit.
520 $a In this work, advanced architectures for high speed, power, and area efficient binary multiplier circuits are presented for use with integer or fixed point operands. First, we present a full multiplier design called the Interlaced Partition Multiplier which is based on partitioning one input number into small groups of bits and interlacing every other partition with zeros. Each partition is multiplied by the other partitions and the presence of the interlaced zeros allows the partial products to be formed by concatenating the products of each partition without carries. Simulations show that multiplier can be built with this design that achieve new trade offs in terms of area and speed cost.
520 $a Next, we present a novel bit stacking technique that can be used to implement binary counters for use in any multiplier topology. This counting technique can be used to build 6:3 and 7:3 Counters that outperform any other binary counter design and also consume less power. To demonstrate the effect of these fast, efficient counters, 64 by 64 bit Counter-Based Wallace Tree multipliers are implemented using existing binary counters and also the proposed counters. Simulations show that these full multiplier designs are faster and consume less power when built using the proposed counters. Thus, the proposed counters yield a pure gain when used to build multiplier circuits.
533 $a Electronic reproduction. $b Ann Arbor, Mich. : $c ProQuest, $d 2018
538 $a Mode of access: World Wide Web
650 4 $a Electrical engineering. $3 596380
650 4 $a Computer engineering. $3 569006
655 7 $a Electronic books. $2 local $3 554714
690 $a 0544
690 $a 0464
710 2 $a ProQuest Information and Learning Co. $3 1178819
710 2 $a State University of New York at Buffalo. $b Electrical Engineering. $3 845470
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=10283377 $z click for full text (PQDT)

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