國立虎尾科技大學 |

Programmable Hardware Acceleration.

紀錄類型:	書目-語言資料,手稿 : Monograph/item
正題名/作者:	Programmable Hardware Acceleration./
作者:	Gangadhar, Vinay.
面頁冊數:	1 online resource (177 pages)
附註:	Source: Dissertation Abstracts International, Volume: 79-04(E), Section: B.
標題:	Computer engineering. -
電子資源:	click for full text (PQDT)
ISBN:	9780355549584

Programmable Hardware Acceleration.
Gangadhar, Vinay.

Programmable Hardware Acceleration. - 1 online resource (177 pages)

Source: Dissertation Abstracts International, Volume: 79-04(E), Section: B.

Thesis (Ph.D.)--The University of Wisconsin - Madison, 2017.

Includes bibliographical references

The rising dark silicon problem and the waning benefits of device scaling has caused a push towards specialization and hardware acceleration in last few years. Recently, computer architects both in industry and academia have followed the trend of building custom high-performance hardware engines for individual application domains, generally called as Domain-Specific Accelerators (DSAs). DSAs have been shown to achieve 10 to 1,000 times performance and energy efficiency improvements over general-purpose and data-parallel architectures for various application domains like machine learning, computer vision, databases and others. While providing these huge benefits, DSAs sacrifice programmability for efficiency and are prone to obsoletion due to domain volatility. The stark trade-offs between efficiency and generality at these two extremes poses an interesting question: Is it possible to have an architecture which has the best of both -- programmability and efficiency, and how close can we get to such a design?

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2018

Mode of access: World Wide Web

ISBN: 9780355549584Subjects--Topical Terms:

569006
Computer engineering.
Index Terms--Genre/Form:

554714
Electronic books.

Programmable Hardware Acceleration.
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245 1 0 $a Programmable Hardware Acceleration.
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300 $a 1 online resource (177 pages)
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500 $a Source: Dissertation Abstracts International, Volume: 79-04(E), Section: B.
500 $a Adviser: Karthikeyan Sankaralingam.
502 $a Thesis (Ph.D.)--The University of Wisconsin - Madison, 2017.
504 $a Includes bibliographical references
520 $a The rising dark silicon problem and the waning benefits of device scaling has caused a push towards specialization and hardware acceleration in last few years. Recently, computer architects both in industry and academia have followed the trend of building custom high-performance hardware engines for individual application domains, generally called as Domain-Specific Accelerators (DSAs). DSAs have been shown to achieve 10 to 1,000 times performance and energy efficiency improvements over general-purpose and data-parallel architectures for various application domains like machine learning, computer vision, databases and others. While providing these huge benefits, DSAs sacrifice programmability for efficiency and are prone to obsoletion due to domain volatility. The stark trade-offs between efficiency and generality at these two extremes poses an interesting question: Is it possible to have an architecture which has the best of both -- programmability and efficiency, and how close can we get to such a design?
520 $a This dissertation explores how far the efficiency of a programmable architecture can be pushed, and whether it can come close to the performance, energy, and area efficiency of a domain-specific based approach. We specifically propose a type of hardware acceleration called "Programmable Hardware Acceleration", with the design, implementation, and evaluation of a hardware accelerator which is programmable using an efficient hardware-software interface and yet achieve efficiency close to DSAs. This work has several observations and key findings. First, we rely on the insight that 'acceleratable' algorithms have common specialization principles and most of the DSAs employ these. Second, these specialization principles can be exploited in a hardware architecture with a right composure of programmable and configurable microarchitectural mechanisms to arrive at a generic programmable hardware accelerator design. Third, the same primitives can also be exposed to the programmers as a hardware-software interface to take benefit of the programmable acceleration. Our evaluation and analysis suggest that a programmable hardware accelerator can achieve performance as close as DSAs with only 2x overheads in area and power. In summary, this work shows a principled approach in building hardware accelerators by pushing the limits of their efficiency while still retaining the programmability.
533 $a Electronic reproduction. $b Ann Arbor, Mich. : $c ProQuest, $d 2018
538 $a Mode of access: World Wide Web
650 4 $a Computer engineering. $3 569006
650 4 $a Computer science. $3 573171
655 7 $a Electronic books. $2 local $3 554714
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690 $a 0984
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710 2 $a The University of Wisconsin - Madison. $b Electrical Engineering. $3 1178889
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=10690203 $z click for full text (PQDT)