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Analysis of IP based implementations of adders and multipliers in submicron and deep submicron technologies.

紀錄類型:	書目-語言資料,手稿 : Monograph/item
正題名/作者:	Analysis of IP based implementations of adders and multipliers in submicron and deep submicron technologies./
作者:	Kurapati, Vijaya Chandra.
面頁冊數:	1 online resource (74 pages)
附註:	Source: Masters Abstracts International, Volume: 47-03, page: 1778.
Contained By:	Masters Abstracts International47-03.
標題:	Electrical engineering. -
電子資源:	click for full text (PQDT)
ISBN:	9780549974727

Analysis of IP based implementations of adders and multipliers in submicron and deep submicron technologies.
Kurapati, Vijaya Chandra.

Analysis of IP based implementations of adders and multipliers in submicron and deep submicron technologies. - 1 online resource (74 pages)

Source: Masters Abstracts International, Volume: 47-03, page: 1778.

Thesis (M.S.)--Oklahoma State University, 2008.

Includes bibliographical references

Scope and Method of Study. Datapath is at the heart of the microprocessor whose performance is a key factor which determines the performance of the processor. Adders and multipliers are the key elements in the datapath which usually are a measure of the performance of the datapath. So, with scaling of MOS transistors down into the deep submicron regime, it is necessary to investigate the performance of these key elements at such small device sizes. This thesis focuses on investigating the performance of existing architectures of adders and multipliers in the submicron and deep submicron technologies at the physical implementation level. Also, an effort has been made to investigate the performance of pipelined implementations of these architectures. Verilog HDL instantiations of adders and multipliers that are available with the DesignWare Building Block IP of Synopsys have been utilized in this thesis. The entire process of the design right from synthesis of the design down to power analysis of the design has been carried out using various EDA tools and has been automated using scripts written in TCL.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2018

Mode of access: World Wide Web

ISBN: 9780549974727Subjects--Topical Terms:

596380
Electrical engineering.
Index Terms--Genre/Form:

554714
Electronic books.

Analysis of IP based implementations of adders and multipliers in submicron and deep submicron technologies.
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245 1 0 $a Analysis of IP based implementations of adders and multipliers in submicron and deep submicron technologies.
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500 $a Source: Masters Abstracts International, Volume: 47-03, page: 1778.
500 $a Adviser: James E. Stine.
502 $a Thesis (M.S.)--Oklahoma State University, 2008.
504 $a Includes bibliographical references
520 $a Scope and Method of Study. Datapath is at the heart of the microprocessor whose performance is a key factor which determines the performance of the processor. Adders and multipliers are the key elements in the datapath which usually are a measure of the performance of the datapath. So, with scaling of MOS transistors down into the deep submicron regime, it is necessary to investigate the performance of these key elements at such small device sizes. This thesis focuses on investigating the performance of existing architectures of adders and multipliers in the submicron and deep submicron technologies at the physical implementation level. Also, an effort has been made to investigate the performance of pipelined implementations of these architectures. Verilog HDL instantiations of adders and multipliers that are available with the DesignWare Building Block IP of Synopsys have been utilized in this thesis. The entire process of the design right from synthesis of the design down to power analysis of the design has been carried out using various EDA tools and has been automated using scripts written in TCL.
520 $a Findings and Conclusions. Various architectures of adders and multipliers available with the DesignWare Building Block IP were implemented in different technologies for various bit widths. Adders and multipliers were implemented in unpipelined and two-stage pipelined configurations. These design implementations were analyzed for key parameters of total dynamic power, leakage power, Energy-Delay product, delay and area at various bit widths. Using the results obtained optimal implementations of adders and multipliers for before mentioned key parameters were summarized. These results were consistent for all implemented bit widths in all implemented technologies. Also, the leakage power was seen to contribute a higher percentage to the value of the average power dissipation in deep submicron technologies when compared to submicron technologies.
533 $a Electronic reproduction. $b Ann Arbor, Mich. : $c ProQuest, $d 2018
538 $a Mode of access: World Wide Web
650 4 $a Electrical engineering. $3 596380
655 7 $a Electronic books. $2 local $3 554714
690 $a 0544
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710 2 $a Oklahoma State University. $b Electrical Engineering. $3 1182179
773 0 $t Masters Abstracts International $g 47-03.
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