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Design of switched-capacitor and switched-current pipelined analog-to-digital converters in 0.18um CMOS technology.

紀錄類型:	書目-語言資料,手稿 : Monograph/item
正題名/作者:	Design of switched-capacitor and switched-current pipelined analog-to-digital converters in 0.18um CMOS technology./
作者:	Dalrymple, Joseph.
面頁冊數:	1 online resource (45 pages)
附註:	Source: Masters Abstracts International, Volume: 47-04, page: 2302.
Contained By:	Masters Abstracts International47-04.
標題:	Electrical engineering. -
電子資源:	click for full text (PQDT)
ISBN:	9781109034066

Design of switched-capacitor and switched-current pipelined analog-to-digital converters in 0.18um CMOS technology.
Dalrymple, Joseph.

Design of switched-capacitor and switched-current pipelined analog-to-digital converters in 0.18um CMOS technology. - 1 online resource (45 pages)

Source: Masters Abstracts International, Volume: 47-04, page: 2302.

Thesis (M.S.)--California State University, Long Beach, 2008.

Includes bibliographical references

Analog-to-digital converters (ADC) are key design components in digital communication and signal processing systems as they provide the link between the analog world and digital systems. There are many ADC architectures available, each with different advantages and disadvantages. The pipelined ADC is used in this thesis as it possesses a good balance of speed, resolution, and power dissipation. This thesis will put forward two different pipelined ADC designs. One design will be switched capacitor and the other will be switched current. Switched capacitor designs process signals as voltages and store the information as charges on linear capacitors as the switches open and close. Switched current designs, on the other hand, process the signals as currents and store the information on the MOS transistor gate capacitors. The switched capacitor design has a speed of 50MS/s, 6 bit output, SINAD of 36.54 dB, INL of 0.8 LSB, DNL of 0.6 LSB, power of 34mW, and voltage supply of 1.8 volts. The non-boosted switched current design has a speed of 50MS/s, 6 bit output, SINAD of 35.64 dB, INL of 0.62 LSB, DNL of 0.81 LSB, power of 45mW, and voltage supply of 1.8 volts. The boosted switched current design has a speed of 60MS/s, 6 bit output, SINAD of 35.43 dB, INL of 0.74 LSB, DNL of 0.85 LSB, power of 45mW, and voltage supply of 1.8 volts. This thesis uses the 0.18um generic CMOS process from the Cadence design kit.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2018

Mode of access: World Wide Web

ISBN: 9781109034066Subjects--Topical Terms:

596380
Electrical engineering.
Index Terms--Genre/Form:

554714
Electronic books.

Design of switched-capacitor and switched-current pipelined analog-to-digital converters in 0.18um CMOS technology.
LDR:02626ntm a2200313Ki 4500 001 915922
005 20180907134543.5
006 m o u
007 cr mn||||a|a||
008 190606s2008 xx obm 000 0 eng d
020 $a 9781109034066
035 $a (MiAaPQ)AAI1463158
035 $a AAI1463158
040 $a MiAaPQ $b eng $c MiAaPQ $d NTU
100 1 $a Dalrymple, Joseph. $3 1189473
245 1 0 $a Design of switched-capacitor and switched-current pipelined analog-to-digital converters in 0.18um CMOS technology.
264 0 $c 2008
300 $a 1 online resource (45 pages)
336 $a text $b txt $2 rdacontent
337 $a computer $b c $2 rdamedia
338 $a online resource $b cr $2 rdacarrier
500 $a Source: Masters Abstracts International, Volume: 47-04, page: 2302.
500 $a Adviser: I-hung Khoo.
502 $a Thesis (M.S.)--California State University, Long Beach, 2008.
504 $a Includes bibliographical references
520 $a Analog-to-digital converters (ADC) are key design components in digital communication and signal processing systems as they provide the link between the analog world and digital systems. There are many ADC architectures available, each with different advantages and disadvantages. The pipelined ADC is used in this thesis as it possesses a good balance of speed, resolution, and power dissipation. This thesis will put forward two different pipelined ADC designs. One design will be switched capacitor and the other will be switched current. Switched capacitor designs process signals as voltages and store the information as charges on linear capacitors as the switches open and close. Switched current designs, on the other hand, process the signals as currents and store the information on the MOS transistor gate capacitors. The switched capacitor design has a speed of 50MS/s, 6 bit output, SINAD of 36.54 dB, INL of 0.8 LSB, DNL of 0.6 LSB, power of 34mW, and voltage supply of 1.8 volts. The non-boosted switched current design has a speed of 50MS/s, 6 bit output, SINAD of 35.64 dB, INL of 0.62 LSB, DNL of 0.81 LSB, power of 45mW, and voltage supply of 1.8 volts. The boosted switched current design has a speed of 60MS/s, 6 bit output, SINAD of 35.43 dB, INL of 0.74 LSB, DNL of 0.85 LSB, power of 45mW, and voltage supply of 1.8 volts. This thesis uses the 0.18um generic CMOS process from the Cadence design kit.
533 $a Electronic reproduction. $b Ann Arbor, Mich. : $c ProQuest, $d 2018
538 $a Mode of access: World Wide Web
650 4 $a Electrical engineering. $3 596380
655 7 $a Electronic books. $2 local $3 554714
690 $a 0544
710 2 $a ProQuest Information and Learning Co. $3 1178819
710 2 $a California State University, Long Beach. $3 1184465
773 0 $t Masters Abstracts International $g 47-04.
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=1463158 $z click for full text (PQDT)