國立虎尾科技大學 |

Cost-Effective Integrated Wireless Monitoring of Wafer Cleanliness Using SOI Technology.

紀錄類型:	書目-語言資料,手稿 : Monograph/item
正題名/作者:	Cost-Effective Integrated Wireless Monitoring of Wafer Cleanliness Using SOI Technology./
作者:	Pandit, Vedhas.
面頁冊數:	1 online resource (91 pages)
附註:	Source: Masters Abstracts International, Volume: 49-03, page: 1964.
Contained By:	Masters Abstracts International49-03.
標題:	Electrical engineering. -
電子資源:	click for full text (PQDT)
ISBN:	9781124371450

Cost-Effective Integrated Wireless Monitoring of Wafer Cleanliness Using SOI Technology.
Pandit, Vedhas.

Cost-Effective Integrated Wireless Monitoring of Wafer Cleanliness Using SOI Technology. - 1 online resource (91 pages)

Source: Masters Abstracts International, Volume: 49-03, page: 1964.

Thesis (M.S.)--Arizona State University, 2010.

Includes bibliographical references

The thesis focuses on cost-efficient integration of the electro-chemical residue sensor (ECRS), a novel sensor developed for the in situ and real-time measurement of the residual impurities left on the wafer surface and in the fine structures of patterned wafers during typical rinse processes, and wireless transponder circuitry that is based on RFID technology. The proposed technology uses only the NMOS FD-SOI transistors with amorphous silicon as active material with silicon nitride as a gate dielectric. The proposed transistor was simulated under the SILVACO ATLAS Simulation Framework. A parametric study was performed to study the impact of different gate lengths (6 mum to 56 mum), electron motilities (0.1 cm2/Vs to 1 cm2/Vs), gate dielectric (SiO2 and SiNx) and active materials (a-Si and poly-Si) specifications. Level-1 models, that are accurate enough to acquire insight into the circuit behavior and perform preliminary design, were successfully constructed by analyzing drain current and gate to node capacitance characteristics against drain to source and gate to source voltages. Using the model corresponding to SiNx as gate dielectric, a-Si:H as active material with electron mobility equal to 0.4 cm2/V-sec, an operational amplifier was designed and was tested in unity gain configuration at modest load-frequency specifications.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2018

Mode of access: World Wide Web

ISBN: 9781124371450Subjects--Topical Terms:

596380
Electrical engineering.
Index Terms--Genre/Form:

554714
Electronic books.

Cost-Effective Integrated Wireless Monitoring of Wafer Cleanliness Using SOI Technology.
LDR:02548ntm a2200325Ki 4500 001 915929
005 20180907134543.5
006 m o u
007 cr mn||||a|a||
008 190606s2010 xx obm 000 0 eng d
020 $a 9781124371450
035 $a (MiAaPQ)AAI1483475
035 $a (MiAaPQ)asu:10245
035 $a AAI1483475
040 $a MiAaPQ $b eng $c MiAaPQ $d NTU
100 1 $a Pandit, Vedhas. $3 1189481
245 1 0 $a Cost-Effective Integrated Wireless Monitoring of Wafer Cleanliness Using SOI Technology.
264 0 $c 2010
300 $a 1 online resource (91 pages)
336 $a text $b txt $2 rdacontent
337 $a computer $b c $2 rdamedia
338 $a online resource $b cr $2 rdacarrier
500 $a Source: Masters Abstracts International, Volume: 49-03, page: 1964.
500 $a Adviser: Bert Vermeire.
502 $a Thesis (M.S.)--Arizona State University, 2010.
504 $a Includes bibliographical references
520 $a The thesis focuses on cost-efficient integration of the electro-chemical residue sensor (ECRS), a novel sensor developed for the in situ and real-time measurement of the residual impurities left on the wafer surface and in the fine structures of patterned wafers during typical rinse processes, and wireless transponder circuitry that is based on RFID technology. The proposed technology uses only the NMOS FD-SOI transistors with amorphous silicon as active material with silicon nitride as a gate dielectric. The proposed transistor was simulated under the SILVACO ATLAS Simulation Framework. A parametric study was performed to study the impact of different gate lengths (6 mum to 56 mum), electron motilities (0.1 cm2/Vs to 1 cm2/Vs), gate dielectric (SiO2 and SiNx) and active materials (a-Si and poly-Si) specifications. Level-1 models, that are accurate enough to acquire insight into the circuit behavior and perform preliminary design, were successfully constructed by analyzing drain current and gate to node capacitance characteristics against drain to source and gate to source voltages. Using the model corresponding to SiNx as gate dielectric, a-Si:H as active material with electron mobility equal to 0.4 cm2/V-sec, an operational amplifier was designed and was tested in unity gain configuration at modest load-frequency specifications.
533 $a Electronic reproduction. $b Ann Arbor, Mich. : $c ProQuest, $d 2018
538 $a Mode of access: World Wide Web
650 4 $a Electrical engineering. $3 596380
655 7 $a Electronic books. $2 local $3 554714
690 $a 0544
710 2 $a ProQuest Information and Learning Co. $3 1178819
710 2 $a Arizona State University. $b Electrical Engineering. $3 845389
773 0 $t Masters Abstracts International $g 49-03.
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=1483475 $z click for full text (PQDT)