國立虎尾科技大學 |

Fast algorithms for the design and analysis of large power grids.

Record Type:	Language materials, manuscript : Monograph/item
Title/Author:	Fast algorithms for the design and analysis of large power grids./
Author:	Zhong, Yu.
Description:	1 online resource (94 pages)
Notes:	Source: Dissertation Abstracts International, Volume: 69-05, Section: B, page: 3199.
Contained By:	Dissertation Abstracts International69-05B.
Subject:	Electrical engineering. -
Online resource:	click for full text (PQDT)
ISBN:	9780549640066

Fast algorithms for the design and analysis of large power grids.
Zhong, Yu.

Fast algorithms for the design and analysis of large power grids. - 1 online resource (94 pages)

Source: Dissertation Abstracts International, Volume: 69-05, Section: B, page: 3199.

Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2008.

Includes bibliographical references

Careful design and verification of the power grid on a chip are of critical importance to ensure its reliable performance. With the increasing number of transistors on a chip, the size of power grids has grown so large that makes the verification task very challenging. The available computational power and memory resources impose limitation on the size of power grids that can be analyzed using current techniques. In this dissertation, we propose novel algorithms targeted at handling the simulation and design challenges due to the extremely large size and complexity of power grids.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2018

Mode of access: World Wide Web

ISBN: 9780549640066Subjects--Topical Terms:

596380
Electrical engineering.
Index Terms--Genre/Form:

554714
Electronic books.

Fast algorithms for the design and analysis of large power grids.
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100 1 $a Zhong, Yu. $3 1189507
245 1 0 $a Fast algorithms for the design and analysis of large power grids.
264 0 $c 2008
300 $a 1 online resource (94 pages)
336 $a text $b txt $2 rdacontent
337 $a computer $b c $2 rdamedia
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500 $a Source: Dissertation Abstracts International, Volume: 69-05, Section: B, page: 3199.
500 $a Adviser: Martin D. F. Wong.
502 $a Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2008.
504 $a Includes bibliographical references
520 $a Careful design and verification of the power grid on a chip are of critical importance to ensure its reliable performance. With the increasing number of transistors on a chip, the size of power grids has grown so large that makes the verification task very challenging. The available computational power and memory resources impose limitation on the size of power grids that can be analyzed using current techniques. In this dissertation, we propose novel algorithms targeted at handling the simulation and design challenges due to the extremely large size and complexity of power grids.
520 $a The voltage drop in power grids is also called the current-resistance (IR) drop, because it is associated with the electrical resistance (R) and the current flow (I). Although IR drop analysis can be naturally formulated as the problem of solving a linear system, the system is too large to be solved by existing linear solvers. For this problem, we first propose two iterative algorithms based on node-by-node traversals and row-by-row traversals of the power grid, respectively. Our algorithms take full advantage of the special structure of the power grid and guarantee convergence to the exact solutions. Based on that, second-order algorithms are developed to further improve the rate of convergence and shorten the runtime. In order to design scalable algorithms to handle ever increasing power-grid sizes, the most promising approach is to use a "divide-and-conquer" strategy. Therefore, we propose a block-iterative domain-decomposition algorithm which effectively combines the advantages of direct solvers and iterative methods. Moreover, the block-iterative domain-decomposition algorithm can solve the convergence problem of ill-conditioned systems. If the power grid system is ill-conditioned, the traditional iterative methods, including the first and second order algorithms, will encounter difficulty of convergence.
520 $a Due to the positive feedback loop between power grid Joule heating and the linear temperature dependence of resistivity, non-uniform temperature profiles on the power grid in high-performance integrated circuits (IC) influence IR drop in the power grid. Lack of accurate evaluation of thermal effect on the IR drop in the power grid may lead to over-design; or worse, underestimates the IR drop due to increased local temperature. For this, we propose a method to compute the temperature-dependent IR drop on the power grid extremely fast. We present a novel thermal model and a mathematical formulation to compute the temperature profiles on the power grid efficiently.
520 $a The design of power grid becomes even more difficult due to the bottleneck of simulation. We propose algorithms to determine the placement of power pads that minimize not only the worst voltage drop but also the voltage deviation across the power grid. Our algorithm uses simulated annealing to minimize the total cost of voltage drops. The key enabler for efficient optimization is a fast localized node-based iterative method to compute the voltages after each movement of pads. Experimental results show that our algorithm demonstrates good runtime characteristics for power grids with large numbers of pad candidates in multimillion-size circuits.
533 $a Electronic reproduction. $b Ann Arbor, Mich. : $c ProQuest, $d 2018
538 $a Mode of access: World Wide Web
650 4 $a Electrical engineering. $3 596380
655 7 $a Electronic books. $2 local $3 554714
690 $a 0544
710 2 $a ProQuest Information and Learning Co. $3 1178819
710 2 $a University of Illinois at Urbana-Champaign. $3 1184184
773 0 $t Dissertation Abstracts International $g 69-05B.
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3314956 $z click for full text (PQDT)