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System-level synthesis and verification.

Northwestern University.

System-level synthesis and verification.

紀錄類型:	書目-語言資料,手稿 : Monograph/item
正題名/作者:	System-level synthesis and verification./
作者:	Liveris, Nikolaos.
面頁冊數:	1 online resource (250 pages)
附註:	Source: Dissertation Abstracts International, Volume: 69-11, Section: B, page: 7039.
Contained By:	Dissertation Abstracts International69-11B.
標題:	Electrical engineering. -
電子資源:	click for full text (PQDT)
ISBN:	9780549883753

System-level synthesis and verification.
Liveris, Nikolaos.

System-level synthesis and verification. - 1 online resource (250 pages)

Source: Dissertation Abstracts International, Volume: 69-11, Section: B, page: 7039.

Thesis (Ph.D.)--Northwestern University, 2008.

Includes bibliographical references

As device sizes decrease, more functionality can be placed in an integrated circuit. Therefore, the design complexity of these circuits increases. To deal with complexity, designers move to higher abstraction levels. Currently, the highest abstraction level is the system-level. In our work we investigate the synthesis and verification problem at the system-level.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2018

Mode of access: World Wide Web

ISBN: 9780549883753Subjects--Topical Terms:

596380
Electrical engineering.
Index Terms--Genre/Form:

554714
Electronic books.

System-level synthesis and verification.
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035 $a (MiAaPQ)northwestern:2006
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040 $a MiAaPQ $b eng $c MiAaPQ $d NTU
100 1 $a Liveris, Nikolaos. $3 1189534
245 1 0 $a System-level synthesis and verification.
264 0 $c 2008
300 $a 1 online resource (250 pages)
336 $a text $b txt $2 rdacontent
337 $a computer $b c $2 rdamedia
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500 $a Source: Dissertation Abstracts International, Volume: 69-11, Section: B, page: 7039.
500 $a Adviser: Hai Zhou.
502 $a Thesis (Ph.D.)--Northwestern University, 2008.
504 $a Includes bibliographical references
520 $a As device sizes decrease, more functionality can be placed in an integrated circuit. Therefore, the design complexity of these circuits increases. To deal with complexity, designers move to higher abstraction levels. Currently, the highest abstraction level is the system-level. In our work we investigate the synthesis and verification problem at the system-level.
520 $a We examine ways to increase the energy efficiency of specific system-level designs. Moreover, we propose an algorithm to retime a system-level description, so that its performance becomes optimal. Retiming is a powerful synthesis operation that can be used to change the schedule of a design. We investigate the optimization power of synthesis operations, like retiming, and propose a sequence of synthesis operations that is complete for the transformation of sequential circuits.
520 $a The verification problem is hard. Checking equivalence between two designs or checking whether a design satisfies a given assertion is proven to have high computational complexity in the general case. We describe ways to simplify the verification problem. First, we show that the verification problem can be simplified by considering it during synthesis without restricting the optimization power of the synthesis operations. Then we show how abstraction can enable the use of efficient automated verification tools.
533 $a Electronic reproduction. $b Ann Arbor, Mich. : $c ProQuest, $d 2018
538 $a Mode of access: World Wide Web
650 4 $a Electrical engineering. $3 596380
650 4 $a Computer science. $3 573171
655 7 $a Electronic books. $2 local $3 554714
690 $a 0544
690 $a 0984
710 2 $a ProQuest Information and Learning Co. $3 1178819
710 2 $a Northwestern University. $b Electrical and Computer Engineering. $3 1186892
773 0 $t Dissertation Abstracts International $g 69-11B.
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3331129 $z click for full text (PQDT)

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