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Synthesis and verification of digital circuits using functional simulation and Boolean satisfiability.

Record Type:	Language materials, manuscript : Monograph/item
Title/Author:	Synthesis and verification of digital circuits using functional simulation and Boolean satisfiability./
Author:	Plaza, Stephen M.
Description:	1 online resource (171 pages)
Notes:	Source: Dissertation Abstracts International, Volume: 70-01, Section: B, page: 4150.
Contained By:	Dissertation Abstracts International70-01B.
Subject:	Computer science. -
Online resource:	click for full text (PQDT)
ISBN:	9780549993797

Synthesis and verification of digital circuits using functional simulation and Boolean satisfiability.
Plaza, Stephen M.

Synthesis and verification of digital circuits using functional simulation and Boolean satisfiability. - 1 online resource (171 pages)

Source: Dissertation Abstracts International, Volume: 70-01, Section: B, page: 4150.

Thesis (Ph.D.)--University of Michigan, 2008.

Includes bibliographical references

The semiconductor industry has long relied on the steady trend of transistor scaling, that is, the shrinking of the dimensions of silicon transistor devices, as a way to improve the cost and performance of electronic devices. However, several design challenges have emerged as transistors have become smaller. For instance, wires are not scaling as fast as transistors, and delay associated with wires is becoming more significant. Moreover, in the design flow for integrated circuits, accurate modeling of wire-related delay is available only toward the end of the design process, when the physical placement of logic units is known. Consequently, one can only know whether timing performance objectives are satisfied, i.e., if timing closure is achieved, after several design optimizations. Unless timing closure is achieved, expensive and time-consuming design-flow iterations are required. Given the challenges arising from increasingly complex designs, failing to quickly achieve timing closure threatens the ability of designers to produce high-performance chips that can match continually growing consumer demands.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2018

Mode of access: World Wide Web

ISBN: 9780549993797Subjects--Topical Terms:

573171
Computer science.
Index Terms--Genre/Form:

554714
Electronic books.

Synthesis and verification of digital circuits using functional simulation and Boolean satisfiability.
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100 1 $a Plaza, Stephen M. $3 1189549
245 1 0 $a Synthesis and verification of digital circuits using functional simulation and Boolean satisfiability.
264 0 $c 2008
300 $a 1 online resource (171 pages)
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500 $a Source: Dissertation Abstracts International, Volume: 70-01, Section: B, page: 4150.
500 $a Advisers: Igor L. Markov; Valeria M. Bertacco.
502 $a Thesis (Ph.D.)--University of Michigan, 2008.
504 $a Includes bibliographical references
520 $a The semiconductor industry has long relied on the steady trend of transistor scaling, that is, the shrinking of the dimensions of silicon transistor devices, as a way to improve the cost and performance of electronic devices. However, several design challenges have emerged as transistors have become smaller. For instance, wires are not scaling as fast as transistors, and delay associated with wires is becoming more significant. Moreover, in the design flow for integrated circuits, accurate modeling of wire-related delay is available only toward the end of the design process, when the physical placement of logic units is known. Consequently, one can only know whether timing performance objectives are satisfied, i.e., if timing closure is achieved, after several design optimizations. Unless timing closure is achieved, expensive and time-consuming design-flow iterations are required. Given the challenges arising from increasingly complex designs, failing to quickly achieve timing closure threatens the ability of designers to produce high-performance chips that can match continually growing consumer demands.
520 $a In this dissertation, we introduce powerful constraint-guided synthesis optimizations that take into account upcoming timing closure challenges and eliminate expensive design iterations. In particular, we use logic simulation to approximate the behavior of increasingly complex designs leveraging a recently proposed concept, called signatures, which allows us to represent a large fraction of a complex circuit's behavior in a compact data structure. By manipulating these signatures, we can efficiently discover a greater set of valid logic transformations than was previously possible and, as a result, enhance timing optimization. Based on the abstractions enabled through signatures, we propose a comprehensive suite of novel techniques: (1) a fast computation of circuit don't cares that increases restructuring opportunities, (2) a verification methodology to prove the correctness of speculative optimizations that efficiently utilizes the computational power of modern multi-core systems, and (3) a physical synthesis strategy using signatures that re-implements sections of a critical path while minimizing perturbations to the existing placement. Our results indicate that logic simulation is effective in approximating the behavior of complex designs and enables a broader family of optimizations than previous synthesis approaches.
533 $a Electronic reproduction. $b Ann Arbor, Mich. : $c ProQuest, $d 2018
538 $a Mode of access: World Wide Web
650 4 $a Computer science. $3 573171
650 4 $a Electrical engineering. $3 596380
655 7 $a Electronic books. $2 local $3 554714
690 $a 0984
690 $a 0544
710 2 $a ProQuest Information and Learning Co. $3 1178819
710 2 $a University of Michigan. $3 845400
773 0 $t Dissertation Abstracts International $g 70-01B.
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3343187 $z click for full text (PQDT)