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Towards Energy Efficient and Reliable 3D Manycore Chip Enabled by Machine Learning.

Record Type:	Language materials, manuscript : Monograph/item
Title/Author:	Towards Energy Efficient and Reliable 3D Manycore Chip Enabled by Machine Learning./
Author:	Das, Sourav.
Description:	1 online resource (200 pages)
Notes:	Source: Dissertation Abstracts International, Volume: 79-11(E), Section: B.
Contained By:	Dissertation Abstracts International79-11B(E).
Subject:	Electrical engineering. -
Online resource:	click for full text (PQDT)
ISBN:	9780438104037

Towards Energy Efficient and Reliable 3D Manycore Chip Enabled by Machine Learning.
Das, Sourav.

Towards Energy Efficient and Reliable 3D Manycore Chip Enabled by Machine Learning. - 1 online resource (200 pages)

Source: Dissertation Abstracts International, Volume: 79-11(E), Section: B.

Thesis (Ph.D.)--Washington State University, 2018.

Includes bibliographical references

As the demand for high performance and energy efficient computation has increased significantly, manycore chip architectures have emerged as a mainstream solution paradigm. A three-dimensional Network-on-Chip (3D NoC) that takes the advantages of amalgamation of two revolutionary technologies namely the NoC and 3D integration, improves the performance of manycore chip significantly. Existing 3D NoC architectures predominantly follow straightforward extension of regular 2D NoCs and suffer from multi-hop communications. In this context, we propose the design of 3D small-world NoC (3D SWNoC) architecture to overcome the challenges of mesh-based architectures and improve the performance of the chip.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2018

Mode of access: World Wide Web

ISBN: 9780438104037Subjects--Topical Terms:

596380
Electrical engineering.
Index Terms--Genre/Form:

554714
Electronic books.

Towards Energy Efficient and Reliable 3D Manycore Chip Enabled by Machine Learning.
LDR:03916ntm a2200397Ki 4500 001 916881
005 20180928111502.5
006 m o u
007 cr mn||||a|a||
008 190606s2018 xx obm 000 0 eng d
020 $a 9780438104037
035 $a (MiAaPQ)AAI10784159
035 $a (MiAaPQ)wsu:12307
035 $a AAI10784159
040 $a MiAaPQ $b eng $c MiAaPQ $d NTU
100 1 $a Das, Sourav. $3 1190741
245 1 0 $a Towards Energy Efficient and Reliable 3D Manycore Chip Enabled by Machine Learning.
264 0 $c 2018
300 $a 1 online resource (200 pages)
336 $a text $b txt $2 rdacontent
337 $a computer $b c $2 rdamedia
338 $a online resource $b cr $2 rdacarrier
500 $a Source: Dissertation Abstracts International, Volume: 79-11(E), Section: B.
500 $a Advisers: Partha Pratim Pande; Janardhan Rao Doppa.
502 $a Thesis (Ph.D.)--Washington State University, 2018.
504 $a Includes bibliographical references
520 $a As the demand for high performance and energy efficient computation has increased significantly, manycore chip architectures have emerged as a mainstream solution paradigm. A three-dimensional Network-on-Chip (3D NoC) that takes the advantages of amalgamation of two revolutionary technologies namely the NoC and 3D integration, improves the performance of manycore chip significantly. Existing 3D NoC architectures predominantly follow straightforward extension of regular 2D NoCs and suffer from multi-hop communications. In this context, we propose the design of 3D small-world NoC (3D SWNoC) architecture to overcome the challenges of mesh-based architectures and improve the performance of the chip.
520 $a In addition, the performance of 3D SWNoC mainly depends on the placement of cores and links. This is an instance of combinatorial optimization problem, which is computationally intractable and needs intelligent exploration of design space to reach physically plausible and near-optimal designs. We adapt a machine learning-based approach to overcome these computational challenges and design an efficient and robust NoC architecture while ensuring significant reduction in convergence time.
520 $a The anticipated performance gain of 3D NoCs degrades in the presence of TSV failures due to fabrication limitations and workload induced stress. We analyze the reliability concerns associated with 3D ICs. We propose several mitigation techniques to counteract TSV failures, which includes VFI-based power management methodology, spare TSV allocation technique, and adaptive routing strategy. We carry out extensive experiments to characterize their performance to improve both reliability and lifetime of 3D NoCs.
520 $a Recently, monolithic 3D (M3D) integration has been proposed as an alternative to TSV-based 3D integration for designing ultra-low-power and high-performance circuits and systems. The smaller dimensions of monolithic inter-tier vias (MIVs) offer high density integration, flexibility of partitioning logic blocks across multiple tiers resulting in significant reduction of the total wire-length. In this work, we explore the design space of M3D-enabled small-world NoC architectures and present a comparative performance evaluation with TSV-based counterparts.
520 $a Finally, we summarize our contributions and outline some promising directions for future work based on the findings of this work. Future work includes incorporating machine learning approaches for on-chip security analysis and development of online mitigation techniques against external attacks.
533 $a Electronic reproduction. $b Ann Arbor, Mich. : $c ProQuest, $d 2018
538 $a Mode of access: World Wide Web
650 4 $a Electrical engineering. $3 596380
650 4 $a Computer engineering. $3 569006
650 4 $a Artificial intelligence. $3 559380
655 7 $a Electronic books. $2 local $3 554714
690 $a 0544
690 $a 0464
690 $a 0800
710 2 $a ProQuest Information and Learning Co. $3 1178819
710 2 $a Washington State University. $b Electrical Engineering. $3 1182170
773 0 $t Dissertation Abstracts International $g 79-11B(E).
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=10784159 $z click for full text (PQDT)