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Modeling and Simulation of a Semicon...

Shinde, Aditya Ramaji.

Modeling and Simulation of a Semiconductor Manufcaturing Fab for Cycle Time Analysis.

紀錄類型:	書目-語言資料,手稿 : Monograph/item
正題名/作者:	Modeling and Simulation of a Semiconductor Manufcaturing Fab for Cycle Time Analysis./
作者:	Shinde, Aditya Ramaji.
面頁冊數:	1 online resource (105 pages)
附註:	Source: Masters Abstracts International, Volume: 58-01.
Contained By:	Masters Abstracts International58-01(E).
標題:	Industrial engineering. -
電子資源:	click for full text (PQDT)
ISBN:	9780438150546

Modeling and Simulation of a Semiconductor Manufcaturing Fab for Cycle Time Analysis.
Shinde, Aditya Ramaji.

Modeling and Simulation of a Semiconductor Manufcaturing Fab for Cycle Time Analysis. - 1 online resource (105 pages)

Source: Masters Abstracts International, Volume: 58-01.

Thesis (M.S.)--University of Maryland, College Park, 2018.

Includes bibliographical references

The goal of the thesis is to conduct a study of the effects of scheduling policies and machine failures on the manufacturing cycle time of the Integrated Circuit (IC) manufacturing process for two processor chips, namely Skylake and Kabylake, manufactured by Intel. The fab simulation model was developed as First in First Out (FIFO), Shortest Processing Time (SPT), Priority based (PB), and Failure FIFO (machine failures) model, and the average cycle times and queue waiting times under the four scheduling policy models were compared for both the Skylake and Kabylake wafers. The study revealed that scheduling policies SPT and PB increased the average cycle time for Skylake wafers while decreasing the average cycle time for the Kabylake wafers, when compared to the base FIFO model. Machine failures increased the average cycle time for both types of wafers.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2018

Mode of access: World Wide Web

ISBN: 9780438150546Subjects--Topical Terms:

679492
Industrial engineering.
Index Terms--Genre/Form:

554714
Electronic books.

Modeling and Simulation of a Semiconductor Manufcaturing Fab for Cycle Time Analysis.
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245 1 0 $a Modeling and Simulation of a Semiconductor Manufcaturing Fab for Cycle Time Analysis.
264 0 $c 2018
300 $a 1 online resource (105 pages)
336 $a text $b txt $2 rdacontent
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500 $a Source: Masters Abstracts International, Volume: 58-01.
500 $a Adviser: Michael Fu.
502 $a Thesis (M.S.)--University of Maryland, College Park, 2018.
504 $a Includes bibliographical references
520 $a The goal of the thesis is to conduct a study of the effects of scheduling policies and machine failures on the manufacturing cycle time of the Integrated Circuit (IC) manufacturing process for two processor chips, namely Skylake and Kabylake, manufactured by Intel. The fab simulation model was developed as First in First Out (FIFO), Shortest Processing Time (SPT), Priority based (PB), and Failure FIFO (machine failures) model, and the average cycle times and queue waiting times under the four scheduling policy models were compared for both the Skylake and Kabylake wafers. The study revealed that scheduling policies SPT and PB increased the average cycle time for Skylake wafers while decreasing the average cycle time for the Kabylake wafers, when compared to the base FIFO model. Machine failures increased the average cycle time for both types of wafers.
533 $a Electronic reproduction. $b Ann Arbor, Mich. : $c ProQuest, $d 2018
538 $a Mode of access: World Wide Web
650 4 $a Industrial engineering. $3 679492
650 4 $a Engineering. $3 561152
650 4 $a Operations research. $3 573517
655 7 $a Electronic books. $2 local $3 554714
690 $a 0546
690 $a 0537
690 $a 0796
710 2 $a ProQuest Information and Learning Co. $3 1178819
710 2 $a University of Maryland, College Park. $b Systems Engineering. $3 1187459
773 0 $t Masters Abstracts International $g 58-01(E).
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=10793297 $z click for full text (PQDT)

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