國立虎尾科技大學 |

Scalar-Vector GPU Architectures.

紀錄類型:	書目-語言資料,手稿 : Monograph/item
正題名/作者:	Scalar-Vector GPU Architectures./
作者:	Chen, Zhongliang.
面頁冊數:	1 online resource (70 pages)
附註:	Source: Dissertation Abstracts International, Volume: 78-10(E), Section: B.
Contained By:	Dissertation Abstracts International78-10B(E).
標題:	Computer engineering. -
電子資源:	click for full text (PQDT)
ISBN:	9781369806373

Scalar-Vector GPU Architectures.
Chen, Zhongliang.

Scalar-Vector GPU Architectures. - 1 online resource (70 pages)

Source: Dissertation Abstracts International, Volume: 78-10(E), Section: B.

Thesis (Ph.D.)--Northeastern University, 2017.

Includes bibliographical references

Graphics Processing Units (GPUs) have evolved to become high throughput processors for general purpose data-parallel applications. Most GPU execution exploits a Single Instruction Multiple Data (SIMD) model, where a single operation is performed on multiple data at a time. However, neither runtime or hardware pays attention to whether the data components on SIMD lanes are the same or different. When a SIMD unit operates on multiple copies of the same data, redundant computations are generated. The inefficient execution can degrade performance and deteriorate power efficiency.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2018

Mode of access: World Wide Web

ISBN: 9781369806373Subjects--Topical Terms:

569006
Computer engineering.
Index Terms--Genre/Form:

554714
Electronic books.

Scalar-Vector GPU Architectures.
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100 1 $a Chen, Zhongliang. $3 1194179
245 1 0 $a Scalar-Vector GPU Architectures.
264 0 $c 2017
300 $a 1 online resource (70 pages)
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500 $a Source: Dissertation Abstracts International, Volume: 78-10(E), Section: B.
500 $a Adviser: David Kaeli.
502 $a Thesis (Ph.D.)--Northeastern University, 2017.
504 $a Includes bibliographical references
520 $a Graphics Processing Units (GPUs) have evolved to become high throughput processors for general purpose data-parallel applications. Most GPU execution exploits a Single Instruction Multiple Data (SIMD) model, where a single operation is performed on multiple data at a time. However, neither runtime or hardware pays attention to whether the data components on SIMD lanes are the same or different. When a SIMD unit operates on multiple copies of the same data, redundant computations are generated. The inefficient execution can degrade performance and deteriorate power efficiency.
520 $a A significant number of SIMD instructions in GPU compute programs demonstrate scalar characteristics, i.e., they operate on the same data across their active lanes. Treating them as normal SIMD instructions results in inefficient GPU execution. To better serve both scalar and vector operations, we propose a heterogeneous scalar-vector GPU architecture. In this thesis we propose the design of a specialized scalar pipeline to handle scalar instructions efficiently with only a single copy of the data, freeing the SIMD pipeline for normal vector execution. The proposed architecture provides an opportunity to save power by just broadcasting the results of a single computation to multiple outputs. In order to balance scalar and vector units, we propose novel schemes to efficiently resolve scalar-vector data dependencies, schedule warps, and dispatch instructions. Also, we consider the impact of varying warp sizes on our scalar-vector architecture and explore subwarp execution for power efficiency. Finally, we demonstrate that the interconnect and memory subsystem can be the new limiting factor on scalar-vector execution.
533 $a Electronic reproduction. $b Ann Arbor, Mich. : $c ProQuest, $d 2018
538 $a Mode of access: World Wide Web
650 4 $a Computer engineering. $3 569006
655 7 $a Electronic books. $2 local $3 554714
690 $a 0464
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710 2 $a Northeastern University. $b Electrical and Computer Engineering. $3 1182193
773 0 $t Dissertation Abstracts International $g 78-10B(E).
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=10272584 $z click for full text (PQDT)