國立虎尾科技大學 |

Collective Communication-Aware High Performance Network-On-Chip Architectures for Big Data Processing.

紀錄類型:	書目-語言資料,手稿 : Monograph/item
正題名/作者:	Collective Communication-Aware High Performance Network-On-Chip Architectures for Big Data Processing./
作者:	Duraisamy, Karthi.
面頁冊數:	1 online resource (210 pages)
附註:	Source: Dissertation Abstracts International, Volume: 79-08(E), Section: B.
Contained By:	Dissertation Abstracts International79-08B(E).
標題:	Computer engineering. -
電子資源:	click for full text (PQDT)
ISBN:	9780355791914

Collective Communication-Aware High Performance Network-On-Chip Architectures for Big Data Processing.
Duraisamy, Karthi.

Collective Communication-Aware High Performance Network-On-Chip Architectures for Big Data Processing. - 1 online resource (210 pages)

Source: Dissertation Abstracts International, Volume: 79-08(E), Section: B.

Thesis (Ph.D.)--Washington State University, 2017.

Includes bibliographical references

In an era when power constraints and data movement are proving to be significant barriers for high-end computing, manycore architectures offer a low power and highly scalable platform suitable for both data- and compute-intensive applications. The performance of a manycore architecture is highly dependent on the capabilities of its communication backbone, namely the Network on-chip (NoC). An efficient NoC designed for a manycore platform must align the connectivity of the NoC with the application's on-chip traffic patterns.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2018

Mode of access: World Wide Web

ISBN: 9780355791914Subjects--Topical Terms:

569006
Computer engineering.
Index Terms--Genre/Form:

554714
Electronic books.

Collective Communication-Aware High Performance Network-On-Chip Architectures for Big Data Processing.
LDR:03611ntm a2200385Ki 4500 001 920665
005 20181203094031.5
006 m o u
007 cr mn||||a|a||
008 190606s2017 xx obm 000 0 eng d
020 $a 9780355791914
035 $a (MiAaPQ)AAI10636268
035 $a (MiAaPQ)wsu:12178
035 $a AAI10636268
040 $a MiAaPQ $b eng $c MiAaPQ $d NTU
100 1 $a Duraisamy, Karthi. $3 1195532
245 1 0 $a Collective Communication-Aware High Performance Network-On-Chip Architectures for Big Data Processing.
264 0 $c 2017
300 $a 1 online resource (210 pages)
336 $a text $b txt $2 rdacontent
337 $a computer $b c $2 rdamedia
338 $a online resource $b cr $2 rdacarrier
500 $a Source: Dissertation Abstracts International, Volume: 79-08(E), Section: B.
500 $a Adviser: Partha Pratim Pande.
502 $a Thesis (Ph.D.)--Washington State University, 2017.
504 $a Includes bibliographical references
520 $a In an era when power constraints and data movement are proving to be significant barriers for high-end computing, manycore architectures offer a low power and highly scalable platform suitable for both data- and compute-intensive applications. The performance of a manycore architecture is highly dependent on the capabilities of its communication backbone, namely the Network on-chip (NoC). An efficient NoC designed for a manycore platform must align the connectivity of the NoC with the application's on-chip traffic patterns.
520 $a Analysis on the inter-core traffic patterns exhibited by various Big Data applications reveal irregular memory access behaviors that give rise to long-range on-chip communication requirements. In addition to the irregular memory access patterns, many of the modern applications also necessitate dense collective communication capabilities among the on-chip nodes. Under collective communication, either a single source node transmits data to all the other nodes in the system (one-to-all) or all the nodes in the system communicate with a single destination node (all-to-one).
520 $a Wireless NoC is an emerging paradigm to design high bandwidth and energy efficient communication backbone for manycore chips. Previous works show that the wireless links can establish low-latency data-transfers even between physically distant on-chip nodes. In addition, with its inherent broadcast capability, the on-chip wireless links are highly suited to perform efficient collective-communication. Thus, employing on-chip wireless links one can design efficient communication infrastructures for manycore platforms running high performance Big Data processing.
520 $a This dissertation focuses on designing a hybrid (wireline + wireless) network-on-chip architecture (called WiNoC) capable of low-latency collective communication. First, we leverage the knowledge gained from studying small-world graphs to design low hop count WiNoC topologies. Next, we augment the WiNoC with suitable data-transfer mechanisms to ensure a congestion-free high performance NoC.
520 $a On overall, this work indicates on-chip communication challenges arise from manycore Big Data processing and proposes a wireless-enabled high performance and energy efficient NoC capable of addressing these challenges.
533 $a Electronic reproduction. $b Ann Arbor, Mich. : $c ProQuest, $d 2018
538 $a Mode of access: World Wide Web
650 4 $a Computer engineering. $3 569006
650 4 $a Information technology. $3 559429
655 7 $a Electronic books. $2 local $3 554714
690 $a 0464
690 $a 0489
710 2 $a ProQuest Information and Learning Co. $3 1178819
710 2 $a Washington State University. $b Electrical Engineering. $3 1182170
773 0 $t Dissertation Abstracts International $g 79-08B(E).
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=10636268 $z click for full text (PQDT)