國立虎尾科技大學 |

Automatic Cache Partitioning Method for High-level Synthesis.

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Automatic Cache Partitioning Method for High-level Synthesis./
作者:	Jones, Bryant M.
出版者:	Ann Arbor : ProQuest Dissertations & Theses, : 2018,
面頁冊數:	169 p.
附註:	Source: Dissertation Abstracts International, Volume: 79-12(E), Section: B.
Contained By:	Dissertation Abstracts International79-12B(E).
標題:	Computer engineering. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=10751888
ISBN:	9780438184688

Automatic Cache Partitioning Method for High-level Synthesis.
Jones, Bryant M.

Automatic Cache Partitioning Method for High-level Synthesis. - Ann Arbor : ProQuest Dissertations & Theses, 2018 - 169 p.

Source: Dissertation Abstracts International, Volume: 79-12(E), Section: B.

Thesis (Ph.D.)--Oakland University, 2018.

Existing algorithms can be automatically translated from software to hardware using High-Level Synthesis (HLS) allowing for quick prototyping or deployment of embedded designs. HLS has been gaining popularity over the past several years as vendor tools have begun adopting the methodology, making it easily available to developers. High-level software is written with a single main memory in mind whereas hardware designs can take advantage of many parallel memories. For high-performance designs it is important to effectively translate and optimize memory access and architectures. Tools provide optimizations on memory structures targeting data reuse and partitioning, but generally these are applied separately for a given object in memory. Memory access that cannot be effectively optimized is serialized to the memory hindering any further parallelization of the surrounding generated hardware.

ISBN: 9780438184688Subjects--Topical Terms:

569006
Computer engineering.

Automatic Cache Partitioning Method for High-level Synthesis.
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500 $a Source: Dissertation Abstracts International, Volume: 79-12(E), Section: B.
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502 $a Thesis (Ph.D.)--Oakland University, 2018.
520 $a Existing algorithms can be automatically translated from software to hardware using High-Level Synthesis (HLS) allowing for quick prototyping or deployment of embedded designs. HLS has been gaining popularity over the past several years as vendor tools have begun adopting the methodology, making it easily available to developers. High-level software is written with a single main memory in mind whereas hardware designs can take advantage of many parallel memories. For high-performance designs it is important to effectively translate and optimize memory access and architectures. Tools provide optimizations on memory structures targeting data reuse and partitioning, but generally these are applied separately for a given object in memory. Memory access that cannot be effectively optimized is serialized to the memory hindering any further parallelization of the surrounding generated hardware.
520 $a In this work, we present an automated optimization method for creating custom cache memory architectures for HLS-generated designs. Our optimization uses runtime profiling data and is performed at a localized scope. This method combines data reuse savings and memory partitioning to further increase the potential parallelism and alleviate the serialized memory access increasing performance. Comparisons are made against architectures without this optimization and against other HLS caching approaches. Results are presented for several benchmarks from multiple application domains showing this method provides a reduction of up to 89% of the number of execution cycles and 87% of the execution time compared to designs with no caches. Benchmarks are further tested through increasing data sets and external memory latency, and show that this method performs well in both cases. Furthermore, this method is not dependent on the Flowpaths toolchain, and an example is given showing that applying this method to other tools provides similar results and savings.
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