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Integrated circuit design for radiat...

Gaul, Stephen J., (1957-)

Integrated circuit design for radiation environments /

Record Type:	Language materials, printed : Monograph/item
Title/Author:	Integrated circuit design for radiation environments // Stephen J. Gaul ... [et al.].
other author:	Gaul, Stephen J.,
Published:	Hoboken :Wiley, : c2020.,
Description:	xxxviii, 350 p. :ill. ; : 25 cm.;
Subject:	Integrated circuits - Design and construction. -
ISBN:	9781119966340 :

Integrated circuit design for radiation environments /
Integrated circuit design for radiation environments /Stephen J. Gaul ... [et al.]. - Hoboken :Wiley,c2020. - xxxviii, 350 p. :ill. ;25 cm.

Includes bibliographical references and index.

"The authors structure the book so that readers can understand the problem of radiation effects first, then understand the skills of layout design and ciruit design after. Chapter One and Chapter Two introduce semiconductors and radiation environments including space, atmospheric and terrestrial environments. Chapter Three details radiation and semiconductor physics. It discusses elementary particle physics so that readers can see how the areas of semiconductors and fundamental interact. Radioactive decay, field equations and transistors are presented in this section too. Damage mechanisms in semiconductors is covered in Chapter Four, including coverage of radiation damage in silicon devices. This leads on logically to single event effects in the next chapter, covering single event upset (SEU), single event gate rupture (SEGR), single event transient (SET), single event latchup (SEL), and radiation techniques. Chapter Six presents radiation-hard semiconductor process and layout techniques, with information on off-the-shelf process technology, and device specific hardening methods. Helpful SEU semiconductor process solutions for SEU are covered in detail in Chapter Seven. Solutions covered include: wells, p-wells, isolation, triple-well, sub-collectors, deep trench and more. Chapter Eight goes into detail on the area of SEU circuit solutions, while Chapter Nine details latchup semiconductor process solutions. Chapter Ten presents Latchup circuit solutions and concluds with a look at emerging effects in future technologies"--

ISBN: 9781119966340 :NT4429

LCCN: 2019025698Subjects--Topical Terms:

561265
Integrated circuits
--Design and construction.

LC Class. No.: TK7874 / .G379 2019

Dewey Class. No.: 621.3815

Integrated circuit design for radiation environments /
LDR:02259cam a2200229 a 4500 001 939417
005 20191216151757.0
008 200305s2020 njua b 001 0 eng
010 $a 2019025698
020 $a 9781119966340 : $c NT4429
020 $a 9781118701874 (adobe pdf)
020 $a 9781118701850 (epub)
035 $a 21023763
040 $a DLC $b eng $c DLC $d NFU
041 0 # $a eng
042 $a pcc
050 0 0 $a TK7874 $b .G379 2019
082 0 0 $a 621.3815 $2 23
245 0 0 $a Integrated circuit design for radiation environments / $c Stephen J. Gaul ... [et al.].
260 # $a Hoboken : $b Wiley, $c c2020.
300 $a xxxviii, 350 p. : $b ill. ; $c 25 cm.
504 $a Includes bibliographical references and index.
520 # $a "The authors structure the book so that readers can understand the problem of radiation effects first, then understand the skills of layout design and ciruit design after. Chapter One and Chapter Two introduce semiconductors and radiation environments including space, atmospheric and terrestrial environments. Chapter Three details radiation and semiconductor physics. It discusses elementary particle physics so that readers can see how the areas of semiconductors and fundamental interact. Radioactive decay, field equations and transistors are presented in this section too. Damage mechanisms in semiconductors is covered in Chapter Four, including coverage of radiation damage in silicon devices. This leads on logically to single event effects in the next chapter, covering single event upset (SEU), single event gate rupture (SEGR), single event transient (SET), single event latchup (SEL), and radiation techniques. Chapter Six presents radiation-hard semiconductor process and layout techniques, with information on off-the-shelf process technology, and device specific hardening methods. Helpful SEU semiconductor process solutions for SEU are covered in detail in Chapter Seven. Solutions covered include: wells, p-wells, isolation, triple-well, sub-collectors, deep trench and more. Chapter Eight goes into detail on the area of SEU circuit solutions, while Chapter Nine details latchup semiconductor process solutions. Chapter Ten presents Latchup circuit solutions and concluds with a look at emerging effects in future technologies"-- $c Provided by publisher.
650 # 0 $a Integrated circuits $x Design and construction. $3 561265
650 # 0 $a Semiconductors $x Effect of radiation on. $3 886807
700 1 # $a Gaul, Stephen J., $d 1957- $3 1225289