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Designing with Xilinx FPGAs = using ...

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Designing with Xilinx FPGAs = using Vivado /

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Designing with Xilinx FPGAs/ edited by Sanjay Churiwala.
其他題名:	using Vivado /
其他作者:	Churiwala, Sanjay.
出版者:	Cham :Springer International Publishing : : 2017.,
面頁冊數:	x, 260 p. :ill., digital ; : 24 cm.;
Contained By:	Springer eBooks
標題:	Field programmable gate arrays. -
電子資源:	http://dx.doi.org/10.1007/978-3-319-42438-5
ISBN:	9783319424385

Designing with Xilinx FPGAs = using Vivado /
Designing with Xilinx FPGAsusing Vivado /[electronic resource] :edited by Sanjay Churiwala. - Cham :Springer International Publishing :2017. - x, 260 p. :ill., digital ;24 cm.

State of the Art Programmable Logic -- Vivado Design Tools -- IP Flows -- Gigabit Transceivers -- Memory Controllers -- Processor Options -- Vivado IP Integrator -- SysGen for DSP -- Synthesis -- C Based Design -- Simulation -- Clocking -- Stacked Silicon Interconnect -- Timing Closure -- Power Analysis and Optimization -- System Monitor -- Hardware Debug -- Emulation Using FPGAs -- Partial Reconfiguration & Hierarchical Design.

ISBN: 9783319424385

Standard No.: 10.1007/978-3-319-42438-5doiSubjects--Uniform Titles:

Vivado Design Suite.
Subjects--Topical Terms:

564014
Field programmable gate arrays.

LC Class. No.: TK7895.G36 / D47 2017

Dewey Class. No.: 621.395

Designing with Xilinx FPGAs = using Vivado /
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505 0 $a State of the Art Programmable Logic -- Vivado Design Tools -- IP Flows -- Gigabit Transceivers -- Memory Controllers -- Processor Options -- Vivado IP Integrator -- SysGen for DSP -- Synthesis -- C Based Design -- Simulation -- Clocking -- Stacked Silicon Interconnect -- Timing Closure -- Power Analysis and Optimization -- System Monitor -- Hardware Debug -- Emulation Using FPGAs -- Partial Reconfiguration & Hierarchical Design.
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