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Innovations in the memory system /

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Innovations in the memory system // Rajeev Balasubramonian.
作者:	Balasubramonian, Rajeev,
其他作者:	Enright Jerger, Natalie.
面頁冊數:	1 PDF (xxi, 129 pages) :illustrations (some color). :
附註:	Part of: Synthesis digital library of engineering and computer science.
標題:	Memory management (Computer science) -
電子資源:	https://doi.org/10.2200/S00933ED1V01Y201906CAC048
電子資源:	https://ieeexplore.ieee.org/servlet/opac?bknumber=8834387
ISBN:	9781627059695

Innovations in the memory system /
Balasubramonian, Rajeev,1977-

Innovations in the memory system /Rajeev Balasubramonian. - 1 PDF (xxi, 129 pages) :illustrations (some color). - Synthesis lectures on computer architecture,#481935-3243 ;. - Synthesis digital library of engineering and computer science..

Part of: Synthesis digital library of engineering and computer science.

Includes bibliographical references (pages 105-128).

1. Introduction -- 2. Memory system basics for every architect -- 2.1. Dram vs. SRAM -- 2.2. Memory channel -- 2.3. DDR standards -- 2.4. DIMMS, ranks, banks, mats -- 2.5. Row buffers -- 2.6. Capacity vs. energy -- 2.7. Address mapping -- 2.8. Scheduling -- 2.9. Dram timing parameters

Abstract freely available; full-text restricted to subscribers or individual document purchasers.

Compendex

The memory system has the potential to be a hub for future innovation. While conventional memory systems focused primarily on high density, other memory system metrics like energy, security, and reliability are grabbing modern research headlines. With processor performance stagnating, it is also time to consider new programming models that move some application computations into the memory system. This, in turn, will lead to feature-rich memory systems with new interfaces. The past decade has seen a number of memory system innovations that point to this future where the memory system will be much more than dense rows of unintelligent bits. This book takes a tour through recent and prominent research works, touching upon new DRAM chip designs and technologies, near data processing approaches, new memory channel architectures, techniques to tolerate the overheads of refresh and fault tolerance, security attacks and mitigations, and memory scheduling.

Mode of access: World Wide Web.

ISBN: 9781627059695

Standard No.: 10.2200/S00933ED1V01Y201906CAC048doiSubjects--Topical Terms:

719496
Memory management (Computer science)
Subjects--Index Terms:

memory system architecture

LC Class. No.: QA76.9.M45 / B355 2019eb

Dewey Class. No.: 005.4/35

Innovations in the memory system /
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100 1 $a Balasubramonian, Rajeev, $d 1977- $e author. $3 1253128
245 1 0 $a Innovations in the memory system / $c Rajeev Balasubramonian.
264 1 $a [San Rafael, California] : $b Morgan & Claypool, $c [2019]
300 $a 1 PDF (xxi, 129 pages) : $b illustrations (some color).
336 $a text $2 rdacontent
337 $a electronic $2 isbdmedia
338 $a online resource $2 rdacarrier
490 1 $a Synthesis lectures on computer architecture, $x 1935-3243 ; $v #48
500 $a Part of: Synthesis digital library of engineering and computer science.
504 $a Includes bibliographical references (pages 105-128).
505 0 $a 1. Introduction -- 2. Memory system basics for every architect -- 2.1. Dram vs. SRAM -- 2.2. Memory channel -- 2.3. DDR standards -- 2.4. DIMMS, ranks, banks, mats -- 2.5. Row buffers -- 2.6. Capacity vs. energy -- 2.7. Address mapping -- 2.8. Scheduling -- 2.9. Dram timing parameters
505 8 $a 3. Commercial memory products -- 3.1. Basic DDR3/DDR4 channels and DIMMS -- 3.2. DDR deviations for higher capacity and bandwidth
505 8 $a 4. Memory scheduling -- 4.1. Memory scheduler basics -- 4.2. Early multi-core memory schedulers -- 4.3. Co-designed schedulers -- 4.4. Discussion
505 8 $a 5. Data placement -- 5.1. Data interleaving -- 5.2. Memory compression -- 5.3. Discussion
505 8 $a 6. Memory chip microarchitectures -- 6.1. Basics of DRAM chip microarchitecture -- 6.2. DRAM chip innovations -- 6.3. Discussion
505 8 $a 7. Memory channels -- 7.1. The basics of parallel and serial interconnects -- 7.2. Memory interconnect innovations
505 8 $a 8. Memory reliability -- 8.1. Basics of dram errors -- 8.2. Memory reliability innovations -- 8.3. Discussion
505 8 $a 9. Memory refresh -- 9.1. Refresh basics -- 9.2. Refresh innovations -- 9.3. Discussion
505 8 $a 10. Near data processing -- 10.1. NDP implementations -- 10.2. In-situ implementations -- 10.3. Programming models and applications -- 10.4. Discussion
505 8 $a 11. Memory security -- 11.1. Memory timing channels -- 11.2. Oblivious RAM (ORAM) -- 11.3. Memory integrity -- 11.4. Impact of smart memories -- 11.5. Other memory security issues -- 11.6. Discussion -- 12. Closing thoughts.
506 $a Abstract freely available; full-text restricted to subscribers or individual document purchasers.
510 0 $a Compendex
510 0 $a INSPEC
510 0 $a Google scholar
510 0 $a Google book search
520 $a The memory system has the potential to be a hub for future innovation. While conventional memory systems focused primarily on high density, other memory system metrics like energy, security, and reliability are grabbing modern research headlines. With processor performance stagnating, it is also time to consider new programming models that move some application computations into the memory system. This, in turn, will lead to feature-rich memory systems with new interfaces. The past decade has seen a number of memory system innovations that point to this future where the memory system will be much more than dense rows of unintelligent bits. This book takes a tour through recent and prominent research works, touching upon new DRAM chip designs and technologies, near data processing approaches, new memory channel architectures, techniques to tolerate the overheads of refresh and fault tolerance, security attacks and mitigations, and memory scheduling.
530 $a Also available in print.
538 $a Mode of access: World Wide Web.
538 $a System requirements: Adobe Acrobat Reader.
588 $a Title from PDF title page (viewed on September 27, 2019).
650 0 $a Memory management (Computer science) $3 719496
650 0 $a Systems software. $3 805433
653 $a memory system architecture
653 $a DRAM
653 $a memory controllers
653 $a memory channels
653 $a low-power memory
653 $a memory security
653 $a error correction codes
653 $a memory reliability
653 $a DRAM refresh
653 $a near data processing
653 $a 3D stacking
700 1 $a Enright Jerger, Natalie. $3 1253129
700 1 $a Martonosi, Margaret. $3 1253130
776 0 8 $i Print version:
830 0 $a Synthesis digital library of engineering and computer science. $3 598254
830 0 $a Synthesis lectures on computer architecture ; $v #48. $3 1253131
856 4 0 $3 Abstract with links to full text $u https://doi.org/10.2200/S00933ED1V01Y201906CAC048
856 4 2 $3 Abstract with links to resource $u https://ieeexplore.ieee.org/servlet/opac?bknumber=8834387