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A primer on memory consistency and cache coherence /

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	A primer on memory consistency and cache coherence // Vijay Nagarajan, Daniel J. Sorin, Mark D. Hill, David A. Wood.
作者:	Nagarajan, Vijay,
其他作者:	Sorin, Daniel J.
面頁冊數:	1 PDF (xx, 274 pages) :illustrations. :
附註:	Part of: Synthesis digital library of engineering and computer science.
標題:	Memory management (Computer science) -
電子資源:	https://ieeexplore.ieee.org/servlet/opac?bknumber=9046330
電子資源:	https://doi.org/10.2200/S00962ED2V01Y201910CAC049
ISBN:	9781681737102 (electronic)

A primer on memory consistency and cache coherence /
Nagarajan, Vijay,

A primer on memory consistency and cache coherence /Vijay Nagarajan, Daniel J. Sorin, Mark D. Hill, David A. Wood. - Second edition. - 1 PDF (xx, 274 pages) :illustrations. - Synthesis lectures on computer architecture,#491935-3243 ;. - Synthesis digital library of engineering and computer science..

Part of: Synthesis digital library of engineering and computer science.

Includes bibliographical references.

1. Introduction to consistency and coherence -- 1.1. Consistency (a.k.a., memory consistency, memory consistency model, or memory model) -- 1.2. Coherence (a.k.a., cache coherence) -- 1.3. Consistency and coherence for heterogeneous systems -- 1.4. Specifying and validating memory consistency models and cache coherence -- 1.5. A consistency and coherence quiz -- 1.6. What this primer does not do -- 1.7. References

Abstract freely available; full-text restricted to subscribers or individual document purchasers.

Compendex

Many modern computer systems, including homogeneous and heterogeneous architectures, support shared memory in hardware. In a shared memory system, each of the processor cores may read and write to a single shared address space. For a shared memory machine, the memory consistency model defines the architecturally visible behavior of its memory system. Consistency definitions provide rules about loads and stores (or memory reads and writes) and how they act upon memory. As part of supporting a memory consistency model, many machines also provide cache coherence protocols that ensure that multiple cached copies of data are kept up-to-date. The goal of this primer is to provide readers with a basic understanding of consistency and coherence. This understanding includes both the issues that must be solved as well as a variety of solutions. We present both high-level concepts as well as specific, concrete examples from real-world systems. This second edition reflects a decade of advancements since the first edition and includes, among other more modest changes, two new chapters: one on consistency and coherence for non-CPU accelerators (with a focus on GPUs) and one that points to formal work and tools on consistency and coherence.

Mode of access: World Wide Web.

ISBN: 9781681737102 (electronic)

Standard No.: 10.2200/S00962ED2V01Y201910CAC049doiSubjects--Topical Terms:

719496
Memory management (Computer science)
Subjects--Index Terms:

computer architectureIndex Terms--Genre/Form:

554714
Electronic books.

LC Class. No.: QA76.9.M45 / N347 2020eb

Dewey Class. No.: 005.43

A primer on memory consistency and cache coherence /
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245 1 2 $a A primer on memory consistency and cache coherence / $c Vijay Nagarajan, Daniel J. Sorin, Mark D. Hill, David A. Wood.
250 $a Second edition.
264 1 $a [San Rafael, California] : $b Morgan & Claypool, $c [2020]
300 $a 1 PDF (xx, 274 pages) : $b illustrations.
336 $a text $2 rdacontent
337 $a electronic $2 isbdmedia
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490 1 $a Synthesis lectures on computer architecture, $x 1935-3243 ; $v #49
500 $a Part of: Synthesis digital library of engineering and computer science.
504 $a Includes bibliographical references.
505 0 $a 1. Introduction to consistency and coherence -- 1.1. Consistency (a.k.a., memory consistency, memory consistency model, or memory model) -- 1.2. Coherence (a.k.a., cache coherence) -- 1.3. Consistency and coherence for heterogeneous systems -- 1.4. Specifying and validating memory consistency models and cache coherence -- 1.5. A consistency and coherence quiz -- 1.6. What this primer does not do -- 1.7. References
505 8 $a 2. Coherence basics -- 2.1. Baseline system model -- 2.2. The problem : how incoherence could possibly occur -- 2.3. The cache coherence interface -- 2.4. (Consistency-agnostic) coherence invariants -- 2.5. References
505 8 $a 3. Memory consistency motivation and sequential consistency -- 3.1. Problems with shared memory behavior -- 3.2. What is a memory consistency model? -- 3.3. Consistency vs. coherence -- 3.4. Basic idea of sequential consistency (SC) -- 3.5. A little SC formalism -- 3.6. Naive SC implementations -- 3.7. A basic SC implementation with cache coherence -- 3.8. Optimized SC implementations with cache coherence -- 3.9. Atomic operations with SC -- 3.10. Putting it all together : MIPS R10000 -- 3.11. Further reading regarding SC -- 3.12. References
505 8 $a 4. Total store order and the x86 memory model -- 4.1. Motivation for TSO/x86 -- 4.2. Basic idea of TSO/x86 -- 4.3. A little TSO/x86 formalism -- 4.4. Implementing TSO/x86 -- 4.5. Further reading regarding TSO -- 4.6. Comparing SC and TSO -- 4.7. References
505 8 $a 5. Relaxed memory consistency -- 5.1. Motivation -- 5.2. An example relaxed consistency model (XC) -- 5.3. Implementing XC -- 5.4. Sequential consistency for data-race-free programs -- 5.5. Some relaxed model concepts -- 5.6. Relaxed memory model case studies -- 5.7. Further reading and commercial relaxed memory models -- 5.8. Comparing memory models -- 5.9. High-level language models -- 5.10. References
505 8 $a 6. Coherence protocols -- 6.1. The big picture -- 6.2. Specifying coherence protocols -- 6.3. Example of a simple coherence protocol -- 6.4. Overview of coherence protocol design space -- 6.5. References
505 8 $a 7. Snooping coherence protocols -- 7.1. Introduction to snooping -- 7.2. Baseline snooping protocol -- 7.3. Adding the exclusive state -- 7.4. Adding the owned state -- 7.5. Non-atomic bus -- 7.6. Optimizations to the bus interconnection network -- 7.7. Case studies -- 7.8. Discussion and the future of snooping -- 7.9. References
505 8 $a 8. Directory coherence protocols -- 8.1. Introduction to directory protocols -- 8.2. Baseline directory system -- 8.3. Adding the exclusive state -- 8.4. Adding the owned state -- 8.5. Representing directory state -- 8.6. Directory organization -- 8.7. Performance and scalability optimizations -- 8.8. Case studies -- 8.9. Discussion and the future of directory protocols -- 8.10. References
505 8 $a 9. Advanced topics in coherence -- 9.1. System models -- 9.2. Performance optimizations -- 9.3. Maintaining liveness -- 9.4. Token coherence -- 9.5. The future of coherence -- 9.6. References
505 8 $a 10. Consistency and coherence for heterogeneous systems -- 10.1. GPU consistency and coherence -- 10.2. More heterogeneity than just GPUs -- 10.3. Further reading -- 10.4. References
505 8 $a 11. Specifying and validating memory consistency models and cache coherence -- 11.1. Specification -- 11.2. Exploring the behavior of memory consistency models -- 11.3. Validating implementations -- 11.4. History and further reading -- 11.5. References.
506 $a Abstract freely available; full-text restricted to subscribers or individual document purchasers.
510 0 $a Compendex
510 0 $a INSPEC
510 0 $a Google scholar
510 0 $a Google book search
520 $a Many modern computer systems, including homogeneous and heterogeneous architectures, support shared memory in hardware. In a shared memory system, each of the processor cores may read and write to a single shared address space. For a shared memory machine, the memory consistency model defines the architecturally visible behavior of its memory system. Consistency definitions provide rules about loads and stores (or memory reads and writes) and how they act upon memory. As part of supporting a memory consistency model, many machines also provide cache coherence protocols that ensure that multiple cached copies of data are kept up-to-date. The goal of this primer is to provide readers with a basic understanding of consistency and coherence. This understanding includes both the issues that must be solved as well as a variety of solutions. We present both high-level concepts as well as specific, concrete examples from real-world systems. This second edition reflects a decade of advancements since the first edition and includes, among other more modest changes, two new chapters: one on consistency and coherence for non-CPU accelerators (with a focus on GPUs) and one that points to formal work and tools on consistency and coherence.
530 $a Also available in print.
538 $a Mode of access: World Wide Web.
538 $a System requirements: Adobe Acrobat Reader.
588 $a Title from PDF title page (viewed on February 28, 2020).
650 0 $a Memory management (Computer science) $3 719496
650 0 $a Cache memory. $3 894412
653 $a computer architecture
653 $a memory consistency
653 $a cache coherence
653 $a shared memory
653 $a memory systems
653 $a multicore processor
653 $a heterogeneous architecture
653 $a GPU
653 $a accelerators
653 $a semantics
653 $a verification
655 0 $a Electronic books. $2 local $3 554714
700 1 $a Sorin, Daniel J. $3 1253155
700 1 $a Hill, Mark D. $q (Mark Donald) $3 1253156
700 1 $a Wood, David Allen. $3 1253157
776 0 8 $i Print version: $z 9781681737119 $z 9781681737096
830 0 $a Synthesis digital library of engineering and computer science. $3 598254
830 0 $a Synthesis lectures in computer architecture ; $v #41 $3 1137472
856 4 2 $3 Abstract with links to resource $u https://ieeexplore.ieee.org/servlet/opac?bknumber=9046330
856 4 0 $3 Abstract with links to full text $u https://doi.org/10.2200/S00962ED2V01Y201910CAC049