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Microarchitecture of Network-on-Chip...
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Microarchitecture of Network-on-Chip Routers = A Designer's Perspective /
紀錄類型:
書目-語言資料,印刷品 : Monograph/item
正題名/作者:
Microarchitecture of Network-on-Chip Routers/ by Giorgos Dimitrakopoulos, Anastasios Psarras, Ioannis Seitanidis.
其他題名:
A Designer's Perspective /
作者:
Dimitrakopoulos, Giorgos.
其他作者:
Psarras, Anastasios.
面頁冊數:
XIV, 175 p. 134 illus., 77 illus. in color.online resource. :
Contained By:
Springer Nature eBook
標題:
Electronic circuits. -
電子資源:
https://doi.org/10.1007/978-1-4614-4301-8
ISBN:
9781461443018
Microarchitecture of Network-on-Chip Routers = A Designer's Perspective /
Dimitrakopoulos, Giorgos.
Microarchitecture of Network-on-Chip Routers
A Designer's Perspective /[electronic resource] :by Giorgos Dimitrakopoulos, Anastasios Psarras, Ioannis Seitanidis. - 1st ed. 2015. - XIV, 175 p. 134 illus., 77 illus. in color.online resource.
Introduction to network-on-chip design -- Link-level flow control and buffering -- Baseline switching modules and routers -- Arbitration logic -- Pipelined wormhole routers -- Virtual-channel flow control and buffering -- Baseline virtual-channel based switching modules and routers -- High-speed allocators for VC-based routers -- Pipelined virtual-channel-based routers.
This book focuses on the microarchitecture of network-on-chip routers from a designer’s perspective, providing ready-to-use solutions for simple and more sophisticated design cases. All aspects of the design of a network-on-chip router, including flow control, buffering architectures, arbitration and allocation, as well as pipelined organizations, are presented in detail. The authors provide numerous detailed examples and practical abstract models, when necessary. Router micro-architectural options are presented in a step-by-step manner, beginning from basic design principles. Even highly sophisticated design alternatives are categorized and broken down to simpler pieces that can be understood easily and analyzed. This book is an invaluable reference for system, architecture, circuit, and EDA researchers and developers, who are interested in understanding the overall picture of network-on-chip routers' microarchitecture, the associated design challenges, and the available solutions. · Covers all aspects of the microarchitecture of Network-on-Chip routers; · Justifies and explains every design choice that is presented in a ready-to-use manner following a designer’s perspective; · Describes performance-enhancing features in a step-by-step manner; ·Includes detailed examples presenting the flow of information inside the router on a cycle-by-cycle basis, highlighting the operation of each part under regular or worst-case traffic scenarios.
ISBN: 9781461443018
Standard No.: 10.1007/978-1-4614-4301-8doiSubjects--Topical Terms:
563332
Electronic circuits.
LC Class. No.: TK7888.4
Dewey Class. No.: 621.3815
Microarchitecture of Network-on-Chip Routers = A Designer's Perspective /
LDR
:03237nam a22003975i 4500
001
960093
003
DE-He213
005
20200701133130.0
007
cr nn 008mamaa
008
201211s2015 xxu| s |||| 0|eng d
020
$a
9781461443018
$9
978-1-4614-4301-8
024
7
$a
10.1007/978-1-4614-4301-8
$2
doi
035
$a
978-1-4614-4301-8
050
4
$a
TK7888.4
072
7
$a
TJFC
$2
bicssc
072
7
$a
TEC008010
$2
bisacsh
072
7
$a
TJFC
$2
thema
082
0 4
$a
621.3815
$2
23
100
1
$a
Dimitrakopoulos, Giorgos.
$4
aut
$4
http://id.loc.gov/vocabulary/relators/aut
$3
1062410
245
1 0
$a
Microarchitecture of Network-on-Chip Routers
$h
[electronic resource] :
$b
A Designer's Perspective /
$c
by Giorgos Dimitrakopoulos, Anastasios Psarras, Ioannis Seitanidis.
250
$a
1st ed. 2015.
264
1
$a
New York, NY :
$b
Springer New York :
$b
Imprint: Springer,
$c
2015.
300
$a
XIV, 175 p. 134 illus., 77 illus. in color.
$b
online resource.
336
$a
text
$b
txt
$2
rdacontent
337
$a
computer
$b
c
$2
rdamedia
338
$a
online resource
$b
cr
$2
rdacarrier
347
$a
text file
$b
PDF
$2
rda
505
0
$a
Introduction to network-on-chip design -- Link-level flow control and buffering -- Baseline switching modules and routers -- Arbitration logic -- Pipelined wormhole routers -- Virtual-channel flow control and buffering -- Baseline virtual-channel based switching modules and routers -- High-speed allocators for VC-based routers -- Pipelined virtual-channel-based routers.
520
$a
This book focuses on the microarchitecture of network-on-chip routers from a designer’s perspective, providing ready-to-use solutions for simple and more sophisticated design cases. All aspects of the design of a network-on-chip router, including flow control, buffering architectures, arbitration and allocation, as well as pipelined organizations, are presented in detail. The authors provide numerous detailed examples and practical abstract models, when necessary. Router micro-architectural options are presented in a step-by-step manner, beginning from basic design principles. Even highly sophisticated design alternatives are categorized and broken down to simpler pieces that can be understood easily and analyzed. This book is an invaluable reference for system, architecture, circuit, and EDA researchers and developers, who are interested in understanding the overall picture of network-on-chip routers' microarchitecture, the associated design challenges, and the available solutions. · Covers all aspects of the microarchitecture of Network-on-Chip routers; · Justifies and explains every design choice that is presented in a ready-to-use manner following a designer’s perspective; · Describes performance-enhancing features in a step-by-step manner; ·Includes detailed examples presenting the flow of information inside the router on a cycle-by-cycle basis, highlighting the operation of each part under regular or worst-case traffic scenarios.
650
0
$a
Electronic circuits.
$3
563332
650
0
$a
Electronics.
$3
596389
650
0
$a
Microelectronics.
$3
554956
650
0
$a
Microprocessors.
$3
632481
650
1 4
$a
Circuits and Systems.
$3
670901
650
2 4
$a
Electronics and Microelectronics, Instrumentation.
$3
670219
650
2 4
$a
Processor Architectures.
$3
669787
700
1
$a
Psarras, Anastasios.
$4
aut
$4
http://id.loc.gov/vocabulary/relators/aut
$3
1062411
700
1
$a
Seitanidis, Ioannis.
$4
aut
$4
http://id.loc.gov/vocabulary/relators/aut
$3
1062412
710
2
$a
SpringerLink (Online service)
$3
593884
773
0
$t
Springer Nature eBook
776
0 8
$i
Printed edition:
$z
9781461443025
776
0 8
$i
Printed edition:
$z
9781461443001
776
0 8
$i
Printed edition:
$z
9781493945580
856
4 0
$u
https://doi.org/10.1007/978-1-4614-4301-8
912
$a
ZDB-2-ENG
912
$a
ZDB-2-SXE
950
$a
Engineering (SpringerNature-11647)
950
$a
Engineering (R0) (SpringerNature-43712)
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