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Low Power Interconnect Design

Record Type:	Language materials, printed : Monograph/item
Title/Author:	Low Power Interconnect Design/ by Sandeep Saini.
Author:	Saini, Sandeep.
Description:	XVII, 152 p. 111 illus., 12 illus. in color.online resource. :
Contained By:	Springer Nature eBook
Subject:	Electronic circuits. -
Online resource:	https://doi.org/10.1007/978-1-4614-1323-3
ISBN:	9781461413233

Low Power Interconnect Design
Saini, Sandeep.

Low Power Interconnect Design[electronic resource] /by Sandeep Saini. - 1st ed. 2015. - XVII, 152 p. 111 illus., 12 illus. in color.online resource.

Part I Basics of Interconnect Design -- Introduction to Interconnects -- CMOS Buffer -- Part II Buffer and Schmidt trigger Insertion Techniques for Low Power Interconnect Design -- Buffer Insertion as a Solution to Interconnect Issues -- Schmidt Trigger Approach -- Part III Bus Coding Techniques for Low Power Interconnect Design -- Bus Coding Techniques.

This book provides practical solutions for delay and power reduction for on-chip interconnects and buses. It provides an in depth description of the problem of signal delay and extra power consumption, possible solutions for delay and glitch removal, while considering the power reduction of the total system. Coverage focuses on use of the Schmitt Trigger as an alternative approach to buffer insertion for delay and power reduction in VLSI interconnects. In the last section of the book, various bus coding techniques are discussed to minimize delay and power in address and data buses. · Provides practical solutions for delay and power reduction for on-chip interconnects and buses; · Focuses on Deep Sub micron technology devices and interconnects; · Offers in depth analysis of delay, including details regarding crosstalk and parasitics; · Describes use of the Schmitt Trigger as a versatile alternative approach to buffer insertion for delay and power reduction in VLSI interconnects; · Provides detailed simulation results to support the theoretical discussions. · Provides details of delay and power efficient bus coding techniques.

ISBN: 9781461413233

Standard No.: 10.1007/978-1-4614-1323-3doiSubjects--Topical Terms:

563332
Electronic circuits.

LC Class. No.: TK7888.4

Dewey Class. No.: 621.3815

Low Power Interconnect Design
LDR:02912nam a22003975i 4500 001 963228
003 DE-He213
005 20200630022841.0
007 cr nn 008mamaa
008 201211s2015 xxu| s |||| 0|eng d
020 $a 9781461413233 $9 978-1-4614-1323-3
024 7 $a 10.1007/978-1-4614-1323-3 $2 doi
035 $a 978-1-4614-1323-3
050 4 $a TK7888.4
072 7 $a TJFC $2 bicssc
072 7 $a TEC008010 $2 bisacsh
072 7 $a TJFC $2 thema
082 0 4 $a 621.3815 $2 23
100 1 $a Saini, Sandeep. $e author. $4 aut $4 http://id.loc.gov/vocabulary/relators/aut $3 1258172
245 1 0 $a Low Power Interconnect Design $h [electronic resource] / $c by Sandeep Saini.
250 $a 1st ed. 2015.
264 1 $a New York, NY : $b Springer New York : $b Imprint: Springer, $c 2015.
300 $a XVII, 152 p. 111 illus., 12 illus. in color. $b online resource.
336 $a text $b txt $2 rdacontent
337 $a computer $b c $2 rdamedia
338 $a online resource $b cr $2 rdacarrier
347 $a text file $b PDF $2 rda
505 0 $a Part I Basics of Interconnect Design -- Introduction to Interconnects -- CMOS Buffer -- Part II Buffer and Schmidt trigger Insertion Techniques for Low Power Interconnect Design -- Buffer Insertion as a Solution to Interconnect Issues -- Schmidt Trigger Approach -- Part III Bus Coding Techniques for Low Power Interconnect Design -- Bus Coding Techniques.
520 $a This book provides practical solutions for delay and power reduction for on-chip interconnects and buses. It provides an in depth description of the problem of signal delay and extra power consumption, possible solutions for delay and glitch removal, while considering the power reduction of the total system. Coverage focuses on use of the Schmitt Trigger as an alternative approach to buffer insertion for delay and power reduction in VLSI interconnects. In the last section of the book, various bus coding techniques are discussed to minimize delay and power in address and data buses. · Provides practical solutions for delay and power reduction for on-chip interconnects and buses; · Focuses on Deep Sub micron technology devices and interconnects; · Offers in depth analysis of delay, including details regarding crosstalk and parasitics; · Describes use of the Schmitt Trigger as a versatile alternative approach to buffer insertion for delay and power reduction in VLSI interconnects; · Provides detailed simulation results to support the theoretical discussions. · Provides details of delay and power efficient bus coding techniques.
650 0 $a Electronic circuits. $3 563332
650 0 $a Electronics. $3 596389
650 0 $a Microelectronics. $3 554956
650 0 $a Microprocessors. $3 632481
650 1 4 $a Circuits and Systems. $3 670901
650 2 4 $a Electronics and Microelectronics, Instrumentation. $3 670219
650 2 4 $a Processor Architectures. $3 669787
710 2 $a SpringerLink (Online service) $3 593884
773 0 $t Springer Nature eBook
776 0 8 $i Printed edition: $z 9781461413226
776 0 8 $i Printed edition: $z 9781461413240
776 0 8 $i Printed edition: $z 9781493942947
856 4 0 $u https://doi.org/10.1007/978-1-4614-1323-3
912 $a ZDB-2-ENG
912 $a ZDB-2-SXE
950 $a Engineering (SpringerNature-11647)
950 $a Engineering (R0) (SpringerNature-43712)