國立虎尾科技大學 |

Multi-Net Optimization of VLSI Interconnect

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Multi-Net Optimization of VLSI Interconnect/ by Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer.
作者:	Moiseev, Konstantin.
其他作者:	Kolodny, Avinoam.
面頁冊數:	XVI, 233 p. 124 illus., 44 illus. in color.online resource. :
Contained By:	Springer Nature eBook
標題:	Electronic circuits. -
電子資源:	https://doi.org/10.1007/978-1-4614-0821-5
ISBN:	9781461408215

Multi-Net Optimization of VLSI Interconnect
Moiseev, Konstantin.

Multi-Net Optimization of VLSI Interconnect[electronic resource] /by Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer. - 1st ed. 2015. - XVI, 233 p. 124 illus., 44 illus. in color.online resource.

An Overview of the VLSI Interconnect Problem -- Interconnect Aspects in Design Methodology and EDA Tools -- Scaling Dependent Electrical Modeling of Interconnects -- Net-by-Net Wire Optimization -- Multi-Net Sizing and Spacing of Bundle Wires -- Multi-net Sizing and Spacing in General Layouts -- Interconnect Optimization by Net Ordering -- Layout Migration -- Future Directions in Interconnect Optimization.

This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits. • Describes the evolution of interconnect scaling and provides new techniques for layout migration and optimization, focusing on multi-net optimization; • Presents research results that provide a level of design optimization which does not exist in commercially-available design automation software tools; • Includes mathematical properties and conditions for optimality of layout, describes and analyses algorithmic solutions, and supplements analysis with examples taken from state-of-the-art chips. This book addresses an intriguing engineering challenge, namely the design of an enormous maze of wires, which run in about a dozen metal layers above billions of transistors in a modern processor. The physical insight, mathematical rigor and methodological approach described in the book, are essential for engineers and computer architects, as they develop new systems of ever-increasing complexity and migrate them to new generations of device technologies. The Authors of this book didn’t only develop the academic methodologies, but actually developed CAD tools, and implemented their tools and methodologies to design VLSI chips. I had the privilege to work with them. --Mooly Eden, Senior Vice President, Intel Corporation; President, Intel Israel The speed, power, area, and reliability of high performance integrated circuits are determined by the on-chip interconnect. With the publication of this book, an important niche has been filled; that is local and global on-chip interconnect optimization. This book provides a theoretical basis for the practical design of the key issue in modern integrated circuits, the on-chip interconnect. --Eby G. Friedman, Distinguished Professor, University of Rochester.

ISBN: 9781461408215

Standard No.: 10.1007/978-1-4614-0821-5doiSubjects--Topical Terms:

563332
Electronic circuits.

LC Class. No.: TK7888.4

Dewey Class. No.: 621.3815

Multi-Net Optimization of VLSI Interconnect
LDR:04140nam a22003975i 4500 001 963330
003 DE-He213
005 20200706142156.0
007 cr nn 008mamaa
008 201211s2015 xxu| s |||| 0|eng d
020 $a 9781461408215 $9 978-1-4614-0821-5
024 7 $a 10.1007/978-1-4614-0821-5 $2 doi
035 $a 978-1-4614-0821-5
050 4 $a TK7888.4
072 7 $a TJFC $2 bicssc
072 7 $a TEC008010 $2 bisacsh
072 7 $a TJFC $2 thema
082 0 4 $a 621.3815 $2 23
100 1 $a Moiseev, Konstantin. $4 aut $4 http://id.loc.gov/vocabulary/relators/aut $3 1064098
245 1 0 $a Multi-Net Optimization of VLSI Interconnect $h [electronic resource] / $c by Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer.
250 $a 1st ed. 2015.
264 1 $a New York, NY : $b Springer New York : $b Imprint: Springer, $c 2015.
300 $a XVI, 233 p. 124 illus., 44 illus. in color. $b online resource.
336 $a text $b txt $2 rdacontent
337 $a computer $b c $2 rdamedia
338 $a online resource $b cr $2 rdacarrier
347 $a text file $b PDF $2 rda
505 0 $a An Overview of the VLSI Interconnect Problem -- Interconnect Aspects in Design Methodology and EDA Tools -- Scaling Dependent Electrical Modeling of Interconnects -- Net-by-Net Wire Optimization -- Multi-Net Sizing and Spacing of Bundle Wires -- Multi-net Sizing and Spacing in General Layouts -- Interconnect Optimization by Net Ordering -- Layout Migration -- Future Directions in Interconnect Optimization.
520 $a This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits. • Describes the evolution of interconnect scaling and provides new techniques for layout migration and optimization, focusing on multi-net optimization; • Presents research results that provide a level of design optimization which does not exist in commercially-available design automation software tools; • Includes mathematical properties and conditions for optimality of layout, describes and analyses algorithmic solutions, and supplements analysis with examples taken from state-of-the-art chips. This book addresses an intriguing engineering challenge, namely the design of an enormous maze of wires, which run in about a dozen metal layers above billions of transistors in a modern processor. The physical insight, mathematical rigor and methodological approach described in the book, are essential for engineers and computer architects, as they develop new systems of ever-increasing complexity and migrate them to new generations of device technologies. The Authors of this book didn’t only develop the academic methodologies, but actually developed CAD tools, and implemented their tools and methodologies to design VLSI chips. I had the privilege to work with them. --Mooly Eden, Senior Vice President, Intel Corporation; President, Intel Israel The speed, power, area, and reliability of high performance integrated circuits are determined by the on-chip interconnect. With the publication of this book, an important niche has been filled; that is local and global on-chip interconnect optimization. This book provides a theoretical basis for the practical design of the key issue in modern integrated circuits, the on-chip interconnect. --Eby G. Friedman, Distinguished Professor, University of Rochester.
650 0 $a Electronic circuits. $3 563332
650 0 $a Electronics. $3 596389
650 0 $a Microelectronics. $3 554956
650 0 $a Microprocessors. $3 632481
650 1 4 $a Circuits and Systems. $3 670901
650 2 4 $a Electronics and Microelectronics, Instrumentation. $3 670219
650 2 4 $a Processor Architectures. $3 669787
700 1 $a Kolodny, Avinoam. $4 aut $4 http://id.loc.gov/vocabulary/relators/aut $3 1064099
700 1 $a Wimer, Shmuel. $4 aut $4 http://id.loc.gov/vocabulary/relators/aut $3 1064100
710 2 $a SpringerLink (Online service) $3 593884
773 0 $t Springer Nature eBook
776 0 8 $i Printed edition: $z 9781461408222
776 0 8 $i Printed edition: $z 9781461408208
776 0 8 $i Printed edition: $z 9781493942626
856 4 0 $u https://doi.org/10.1007/978-1-4614-0821-5
912 $a ZDB-2-ENG
912 $a ZDB-2-SXE
950 $a Engineering (SpringerNature-11647)
950 $a Engineering (R0) (SpringerNature-43712)