國立虎尾科技大學 |

Advanced Hardware Design for Error Correcting Codes

Record Type:	Language materials, printed : Monograph/item
Title/Author:	Advanced Hardware Design for Error Correcting Codes/ edited by Cyrille Chavet, Philippe Coussy.
other author:	Chavet, Cyrille.
Description:	IX, 192 p. 81 illus., 25 illus. in color.online resource. :
Contained By:	Springer Nature eBook
Subject:	Electronic circuits. -
Online resource:	https://doi.org/10.1007/978-3-319-10569-7
ISBN:	9783319105697

Advanced Hardware Design for Error Correcting Codes
Advanced Hardware Design for Error Correcting Codes[electronic resource] /edited by Cyrille Chavet, Philippe Coussy. - 1st ed. 2015. - IX, 192 p. 81 illus., 25 illus. in color.online resource.

User Needs -- Challenges and Limitations for Very High Throughput Decoder Architectures for Soft-Decoding -- Implementation of Polar Decoders -- Parallel architectures for Turbo Product Codes Decoding -- VLSI implementations of sphere detectors -- Stochastic Decoders for LDPC Codes -- MP-SoC/NoC architectures for error correction -- ASIP design for multi-standard channel decoders -- Hardware design of parallel interleaver architecture: a survey. .

This book provides thorough coverage of error correcting techniques. It includes essential basic concepts and the latest advances on key topics in design, implementation, and optimization of hardware/software systems for error correction. The book’s chapters are written by internationally recognized experts in this field. Topics include evolution of error correction techniques, industrial user needs, architectures, and design approaches for the most advanced error correcting codes (Polar Codes, Non-Binary LDPC, Product Codes, etc). This book provides access to recent results, and is suitable for graduate students and researchers of mathematics, computer science, and engineering. • Examines how to optimize the architecture of hardware design for error correcting codes; • Presents error correction codes from theory to optimized architecture for the current and the next generation standards; • Provides coverage of industrial user needs advanced error correcting techniques. Advanced Hardware Design for Error Correcting Codes includes a foreword by Claude Berrou.

ISBN: 9783319105697

Standard No.: 10.1007/978-3-319-10569-7doiSubjects--Topical Terms:

563332
Electronic circuits.

LC Class. No.: TK7888.4

Dewey Class. No.: 621.3815

Advanced Hardware Design for Error Correcting Codes
LDR:03156nam a22003975i 4500 001 966047
003 DE-He213
005 20200703193651.0
007 cr nn 008mamaa
008 201211s2015 gw | s |||| 0|eng d
020 $a 9783319105697 $9 978-3-319-10569-7
024 7 $a 10.1007/978-3-319-10569-7 $2 doi
035 $a 978-3-319-10569-7
050 4 $a TK7888.4
072 7 $a TJFC $2 bicssc
072 7 $a TEC008010 $2 bisacsh
072 7 $a TJFC $2 thema
082 0 4 $a 621.3815 $2 23
245 1 0 $a Advanced Hardware Design for Error Correcting Codes $h [electronic resource] / $c edited by Cyrille Chavet, Philippe Coussy.
250 $a 1st ed. 2015.
264 1 $a Cham : $b Springer International Publishing : $b Imprint: Springer, $c 2015.
300 $a IX, 192 p. 81 illus., 25 illus. in color. $b online resource.
336 $a text $b txt $2 rdacontent
337 $a computer $b c $2 rdamedia
338 $a online resource $b cr $2 rdacarrier
347 $a text file $b PDF $2 rda
505 0 $a User Needs -- Challenges and Limitations for Very High Throughput Decoder Architectures for Soft-Decoding -- Implementation of Polar Decoders -- Parallel architectures for Turbo Product Codes Decoding -- VLSI implementations of sphere detectors -- Stochastic Decoders for LDPC Codes -- MP-SoC/NoC architectures for error correction -- ASIP design for multi-standard channel decoders -- Hardware design of parallel interleaver architecture: a survey. .
520 $a This book provides thorough coverage of error correcting techniques. It includes essential basic concepts and the latest advances on key topics in design, implementation, and optimization of hardware/software systems for error correction. The book’s chapters are written by internationally recognized experts in this field. Topics include evolution of error correction techniques, industrial user needs, architectures, and design approaches for the most advanced error correcting codes (Polar Codes, Non-Binary LDPC, Product Codes, etc). This book provides access to recent results, and is suitable for graduate students and researchers of mathematics, computer science, and engineering. • Examines how to optimize the architecture of hardware design for error correcting codes; • Presents error correction codes from theory to optimized architecture for the current and the next generation standards; • Provides coverage of industrial user needs advanced error correcting techniques. Advanced Hardware Design for Error Correcting Codes includes a foreword by Claude Berrou.
650 0 $a Electronic circuits. $3 563332
650 0 $a Electrical engineering. $3 596380
650 0 $a Computers. $3 565115
650 1 4 $a Circuits and Systems. $3 670901
650 2 4 $a Communications Engineering, Networks. $3 669809
650 2 4 $a Information Systems and Communication Service. $3 669203
700 1 $a Chavet, Cyrille. $4 edt $4 http://id.loc.gov/vocabulary/relators/edt $3 1063308
700 1 $a Coussy, Philippe. $4 edt $4 http://id.loc.gov/vocabulary/relators/edt $3 682289
710 2 $a SpringerLink (Online service) $3 593884
773 0 $t Springer Nature eBook
776 0 8 $i Printed edition: $z 9783319105680
776 0 8 $i Printed edition: $z 9783319105703
776 0 8 $i Printed edition: $z 9783319355108
856 4 0 $u https://doi.org/10.1007/978-3-319-10569-7
912 $a ZDB-2-ENG
912 $a ZDB-2-SXE
950 $a Engineering (SpringerNature-11647)
950 $a Engineering (R0) (SpringerNature-43712)