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IP Cores Design from Specifications to Production = Modeling, Verification, Optimization, and Protection /

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	IP Cores Design from Specifications to Production/ by Khaled Salah Mohamed.
其他題名:	Modeling, Verification, Optimization, and Protection /
作者:	Mohamed, Khaled Salah.
面頁冊數:	IX, 154 p. 153 illus., 115 illus. in color.online resource. :
Contained By:	Springer Nature eBook
標題:	Electronic circuits. -
電子資源:	https://doi.org/10.1007/978-3-319-22035-2
ISBN:	9783319220352

IP Cores Design from Specifications to Production = Modeling, Verification, Optimization, and Protection /
Mohamed, Khaled Salah.

IP Cores Design from Specifications to ProductionModeling, Verification, Optimization, and Protection /[electronic resource] :by Khaled Salah Mohamed. - 1st ed. 2016. - IX, 154 p. 153 illus., 115 illus. in color.online resource. - Analog Circuits and Signal Processing,1872-082X. - Analog Circuits and Signal Processing,.

1. Introduction -- 2. IP Cores Design from Specifications to Production: Modeling, Verification, Optimization, and Protection -- 3. Analyzing the Trade-off between Different Memory Cores and Controllers -- 4. SOC BUSES AND PERIPHERALS: FEATURES AND ARCHITECTURES -- 5. Verilog for Implementation and Verification -- 6. New Trends in SoC Verification: UVM, Bug Localization, Scan-Chain-Based Methodology, GA-Based Test Generation -- 7. Conclusions.

This book describes the life cycle process of IP cores, from specification to production, including IP modeling, verification, optimization, and protection. Various trade-offs in the design process are discussed, including those associated with many of the most common memory cores, controller IPs and system-on-chip (SoC) buses. Readers will also benefit from the author’s practical coverage of new verification methodologies. such as bug localization, UVM, and scan-chain. A SoC case study is presented to compare traditional verification with the new verification methodologies. · Discusses the entire life cycle process of IP cores, from specification to production, including IP modeling, verification, optimization, and protection; · Introduce a deep introduction for Verilog for both implementation and verification point of view. · Demonstrates how to use IP in applications such as memory controllers and SoC buses. · Describes a new verification methodology called bug localization; · Presents a novel scan-chain methodology for RTL debugging; · Enables readers to employ UVM methodology in straightforward, practical terms.

ISBN: 9783319220352

Standard No.: 10.1007/978-3-319-22035-2doiSubjects--Topical Terms:

563332
Electronic circuits.

LC Class. No.: TK7888.4

Dewey Class. No.: 621.3815

IP Cores Design from Specifications to Production = Modeling, Verification, Optimization, and Protection /
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