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Soft Error Mechanisms, Modeling and Mitigation

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Soft Error Mechanisms, Modeling and Mitigation / by Selahattin Sayil.
作者:	Sayil, Selahattin.
面頁冊數:	XI, 105 p. 81 illus., 35 illus. in color.online resource. :
Contained By:	Springer Nature eBook
標題:	Processor Architectures. -
電子資源:	https://doi.org/10.1007/978-3-319-30607-0
ISBN:	9783319306070

Soft Error Mechanisms, Modeling and Mitigation
Sayil, Selahattin.

Soft Error Mechanisms, Modeling and Mitigation [electronic resource] /by Selahattin Sayil. - 1st ed. 2016. - XI, 105 p. 81 illus., 35 illus. in color.online resource.

Introduction -- Mitigation of Single Event Effects -- Transmission Gate (TG) Based Soft Error Mitigation Methods -- Single Event Soft Error Mechanisms -- Modeling Single Event Crosstalk Noise in Nanometer Technologies -- Modeling of Single Event Coupling Delay and Speedup Effects -- Single Event Upset Hardening of Interconnects -- Soft-Error Aware Power Optimization -- Dynamic Threshold Technique for Soft Error and Soft Delay Mitigation.

This book introduces readers to various radiation soft-error mechanisms such as soft delays, radiation induced clock jitter and pulses, and single event (SE) coupling induced effects. In addition to discussing various radiation hardening techniques for combinational logic, the author also describes new mitigation strategies targeting commercial designs. Coverage includes novel soft error mitigation techniques such as the Dynamic Threshold Technique and Soft Error Filtering based on Transmission gate with varied gate and body bias. The discussion also includes modeling of SE crosstalk noise, delay and speed-up effects. Various mitigation strategies to eliminate SE coupling effects are also introduced. Coverage also includes the reliability of low power energy-efficient designs and the impact of leakage power consumption optimizations on soft error robustness. The author presents an analysis of various power optimization techniques, enabling readers to make design choices that reduce static power consumption and improve soft error reliability at the same time. .

ISBN: 9783319306070

Standard No.: 10.1007/978-3-319-30607-0doiSubjects--Topical Terms:

669787
Processor Architectures.

LC Class. No.: TK7888.4

Dewey Class. No.: 621.3815

Soft Error Mechanisms, Modeling and Mitigation
LDR:02846nam a22003975i 4500 001 977993
003 DE-He213
005 20200701020243.0
007 cr nn 008mamaa
008 201211s2016 gw | s |||| 0|eng d
020 $a 9783319306070 $9 978-3-319-30607-0
024 7 $a 10.1007/978-3-319-30607-0 $2 doi
035 $a 978-3-319-30607-0
050 4 $a TK7888.4
072 7 $a TJFC $2 bicssc
072 7 $a TEC008010 $2 bisacsh
072 7 $a TJFC $2 thema
082 0 4 $a 621.3815 $2 23
100 1 $a Sayil, Selahattin. $4 aut $4 http://id.loc.gov/vocabulary/relators/aut $3 1106020
245 1 0 $a Soft Error Mechanisms, Modeling and Mitigation $h [electronic resource] / $c by Selahattin Sayil.
250 $a 1st ed. 2016.
264 1 $a Cham : $b Springer International Publishing : $b Imprint: Springer, $c 2016.
300 $a XI, 105 p. 81 illus., 35 illus. in color. $b online resource.
336 $a text $b txt $2 rdacontent
337 $a computer $b c $2 rdamedia
338 $a online resource $b cr $2 rdacarrier
347 $a text file $b PDF $2 rda
505 0 $a Introduction -- Mitigation of Single Event Effects -- Transmission Gate (TG) Based Soft Error Mitigation Methods -- Single Event Soft Error Mechanisms -- Modeling Single Event Crosstalk Noise in Nanometer Technologies -- Modeling of Single Event Coupling Delay and Speedup Effects -- Single Event Upset Hardening of Interconnects -- Soft-Error Aware Power Optimization -- Dynamic Threshold Technique for Soft Error and Soft Delay Mitigation.
520 $a This book introduces readers to various radiation soft-error mechanisms such as soft delays, radiation induced clock jitter and pulses, and single event (SE) coupling induced effects. In addition to discussing various radiation hardening techniques for combinational logic, the author also describes new mitigation strategies targeting commercial designs. Coverage includes novel soft error mitigation techniques such as the Dynamic Threshold Technique and Soft Error Filtering based on Transmission gate with varied gate and body bias. The discussion also includes modeling of SE crosstalk noise, delay and speed-up effects. Various mitigation strategies to eliminate SE coupling effects are also introduced. Coverage also includes the reliability of low power energy-efficient designs and the impact of leakage power consumption optimizations on soft error robustness. The author presents an analysis of various power optimization techniques, enabling readers to make design choices that reduce static power consumption and improve soft error reliability at the same time. .
650 2 4 $a Processor Architectures. $3 669787
650 0 $a Electronic circuits. $3 563332
650 0 $a Microprocessors. $3 632481
650 1 4 $a Circuits and Systems. $3 670901
650 2 4 $a Electronic Circuits and Devices. $3 782968
710 2 $a SpringerLink (Online service) $3 593884
773 0 $t Springer Nature eBook
776 0 8 $i Printed edition: $z 9783319306063
776 0 8 $i Printed edition: $z 9783319306087
776 0 8 $i Printed edition: $z 9783319808482
856 4 0 $u https://doi.org/10.1007/978-3-319-30607-0
912 $a ZDB-2-ENG
912 $a ZDB-2-SXE
950 $a Engineering (SpringerNature-11647)
950 $a Engineering (R0) (SpringerNature-43712)